The objective of the research is to develop design technologies that can alleviate the general robustness issues of the next-generation nonvolatile memories while maintaining and even improving the generic memory specifications such as density, power and performance. Comprehensive solutions are integrated from architecture, circuit and device layers for the improvement on the density, cost and reliability of emerging nonvolatile memories.
The design techniques include 1) a new write endurance improvement technique for multi-level cell devices to prolong the lifetime of the new nonvolatile memories by applying the coding and wear-leveling techniques that are monitored and controlled by self-contained circuits; 2) self-reference and other adaptive sensing techniques to overcome the impacts of process variations and device wear-out mechanisms for yield improvement.; and 3) a new interleaved 3D-stacking memory integration scheme and peripheral circuit design to increase the number of stacks integrated within a certain height.
The broader impact of the research lies in revealing the importance of applying cross-layer design techniques to resolve the robustness issues of the next-generation NVMs and the attentions to the robust design context. The system architects, the circuit designers and the device integration engineers can be well bridged and educated by the research innovations. The developed techniques can be directly transferred to industry applications under the close collaborations with several industry partners, and directly impact the future computing systems.
| Senior Personnel: | Prof. Hai (Helen) Li (PI) and Prof. Yiran Chen (PI) |
| Sponsors: | National Science Foundation (Prof. Li’s Award) National Science Foundation (Prof. Chen’s Award) |
| Team Members: | Xiuyuan Bi, Yi-Chung Chen, Sicheng Li, Chenchen Liu, Mengjie Mao, Zhenyu Sun, Peiyuan Wang, Wujie Wen, and Yaojun Zhang |
| Collaborators: | Dr. Rajiv Joshi, IBM T. J. Watson Research Center Prof. Guangyu Sun, Peking University Dr. Xiaobin Wang, Avalanche Technology Prof. Weng-Fai Wong, National University of Singapore Prof. Yuan Xie, University of California, Santa Barbara Prof. Tong Zhang, Rensselaer Polytechnic Institute Prof. Wei Zhang, The Hong Kong University of Science and Technology |
| Starting Date: | 09/01/2011 |
Related Publications:
[In Press]
[TVLSI-brf]
Y. Zhang, Y. Li, Z. Sun, H. Li, Y. Chen, and Alex K. Jones, “Read Performance: The Newest Barrier in Scaled STT-RAM,” IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, to appear. DOI: 10.1109/TVLSI.2014.2326797.
[2014]
[TNNLS]
M. Hu, H. Li, Y. Chen, Q. Wu, G. Rose, and R. Linderman, “Memristor Crossbar Based Neuromorphic Computing System: A Case Study,” IEEE Transactions on Neural Networks and Learning Systems (TNNLS), vol. 25, no 10, pp. 1864-1878, Oct. 2014. DOI: 10.1109/TNNLS.2013.2296777.
[TVLSI]
Z. Sun, X. Bi, H. Li, W.-F. Wong, and X. Zhu, “STT-RAM Cache Hierarchy with Multi-retention MTJ Designs,” IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol. 22, no. 6, Jun. 2014, pp. 1281-1293. DOI: 10.1109/TVLSI.2013.2267754.
[NVMSA]
I. Bayram and Y. Chen, “NV-TCAM: Alternative Interests and Practices in NVM Designs,” IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), Aug. 2014, to appear. (Invited)
[DAC]
M. Mao, W. Wen, Y. Zhang, H. Li, and Y. Chen, “Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory,” Design Automation Conference (DAC), Jun. 2014, pp. 1-6. DOI: 10.1145/2593069.2593137.
[ASPDAC]
M. Mao, G. Sun, Y. Li, A. Jones, and Y. Chen, “Prefetching Techniques for STT-RAM based Last-level Cache in CMP Systems,” Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2014, pp. 67-72. DOI: 10.1109/ASPDAC.2014.6742868. (Best Paper Nomination)
[ASPDAC]
J. Wang, Y. Tim, W.-F. Wong, Z.-L. Ong, Z. Sun, and H. Li, “A Coherent Hybrid SRAM and STT-RAM L1 Cache Architecture for Shared Memory Multicores,” Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2014, pp. 610-615. (DOI: 10.1109/ASPDAC.2014. 6742958)
[2013]
[TACO]
Y. Li, Y. Zhang, H. Li, Y. Chen, and A. Jones, “C1C: A Configurable, Compiler-guided STT-RAM L1 Cache,” European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC) also ACM Transactions on Architecture and Code Optimization (TACO), vol. 10, no. 4, article 52, Dec. 2013. DOI: 10.1145/2541228.2555308.
[JETC]
Y. Chen, W. Wong, H. Li, C.-K. Koh, Y. Zhang, and W. Wen, “On-chip Caches built on Multi-Level Spin-Transfer Torque RAM Cells and Its Optimizations,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 9, no 2, article 16, May 2013. DOI: 10.1145/2463585.2463592.
[ICCAD]
Y. Zhang, I. Bayram, Y. Wang, H. Li, and Y. Chen, “ADAMS: Asymmetric Differential STT-RAM Cell Structure for Reliable and High-performance Applications,” International Conference on Computer Aided Design (ICCAD), Nov. 2013, pp. 9-16. DOI: 10.1109/ICCAD.2013.6691091.
[ICCAD]
X. Bi, M. Mao, D. Wang, and H. Li, “Unleashing the Potential of MLC STT-RAM Caches,” International Conference on Computer-Aided Design (ICCAD), Nov. 2013, pp. 429-436. DOI: 10.1109/ICCAD.2013.6691153. (Best Paper Nomination)
[FPL]
Y.-C. Chen, W. Zhang, and H. Li, “A Hardware Security Scheme for RRAM-based FPGA,” International Conference on Field Programmable Logic and Applications (FPL), Aug. 2013, pp. 1-4. DOI: 10.1109/FPL.2013.6645556.
[IJCNN]
F. Ji, H. Li, B. Wysocki, C. Thiem, and N. McDonald “Memristor-based Synapse Design and a Case Study in Reconfigurable Systems,” International Joint Conference on Neural Networks (IJCNN), Aug. 2013, pp. 1-6. DOI: 10.1109/IJCNN.2013.6706776.
[DAC]
Z. Sun, W. Wu, and H. Li, “Cross-Layer Racetrack Memory Design for Ultra High Density and Low Power Consumption,” Design Automation Conference (DAC), Jun. 2013, Article 53. DOI: 10.1145/2463209.2488799.
[GLSVLSI]
M. Mao, H. Li, A. Jones, and Y. Chen, “Coordinating Prefetching and STT-RAM-based Last-level Cache Management for Multicore Systems,” Great Lakes Symposium on VLSI (GLVLSI), May 2013, pp. 55-60. DOI: 10.1145/2483028.2483060. (Best Paper Award)
[DATE]
X. Bi, A. M. Weldon, and H. Li, “STT-RAM Designs Supporting Dual-port Accesses,” Design, Automation & Test in Europe (DATE), Mar. 2013, pp. 853-858. DOI: 10.7873/DATE.2013.180.
[ASPDAC]
Q. Li, J. Li, L. Shi, C. J. Xue, Y. Chen, and Y. He, “Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache,” Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2013, pp. 273-278. DOI: 10.1109/ASPDAC.2013.6509608. (Best Paper Nomination)
[ASPDAC]
W. Wen, Y. Zhang, L. Zhang, and Y. Chen, “Loadsa: A Yield-Driven Top-Down Design Method for STT-RAM Array,” Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2013, pp. 291-296. DOI: 10.1109/ASPDAC.2013.6509611.
[DATE-WIP]
J. Li, L. Shi, Q. Li, C. J. Xue, Y. Chen, and Y. Xu, “Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM,” Design, Automation & Test in Europe (DATE), Mar. 2013, pp. 1247-1250. DOI: 10.7873/DATE.2013.258.
[SHAW4-wkp]
M. Mao, H. Li, A. Jones, J. Xue, and Y. Chen, “Dynamic Prefetch Aggressiveness Tuning for STT-RAM-based Last-level Cache,” 4th Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW4), Feb. 2013.
[DAAMC-wkp]
Y. Zhang, *I. Bayram, Y. Wang, H. Li and Y. Chen, “ADAMS: Asymmetric Differential STT-RAM Cell Structure for Reliable and High-performance Applications,” International Workshop on Design Automation for Analog and Mixed-Signal Circuits, Nov. 2013. (Poster)
[2012]
[CRC]
Y. Chen, H. Li, Y. Xie, and D. Niu, Low Power Design of Emerging Memory Technologies, (in Handbook of Energy-Aware and Green Computing. Editors: Ishfaq Ahmad and Sanjay Ranka), CRC Press, Jan. 24, 2012. ISBN: 978-14-398-5040-4.
[TVLSI]
Z. Sun, H. Li, Y. Chen, and X. Wang, “Voltage Driven Non-Destructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory,” IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol. 20, no. 11, Nov. 2012, pp. 2020-2030. DOI: 10.1109/TVLSI.2011.2166282.
[TMAG]
Y. Zhang, W. Wen, and Y. Chen, “The Prospect of STT-RAM Scaling from Readability Perspective,” IEEE Transaction on Magnetics (TMAG), vol. 48, no. 11, Nov. 2012, pp. 3035-3038. DOI: 10.1109/ TMAG.2012.2203589.
[JAP]
Z. Sun, H. Li, and X. Wang, “MTJ Design Margin Exploration for Self-Reference Sensing,” Journal of Applied Physics (JAP), vol. 111, Mar. 2012, (07C726). DOI: 10.1063/1.3679647.
[JSSC]
Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu and T. Zhang, “A 130nm 1.2V/3.3V 16Kb Spin-Transfer Torque Random Access Memory with Nondestructive Self-Reference Sensing Scheme,” IEEE Journal of Solid State Circuits (JSSC), vol. 47, no.2, Feb. 2012, pp. 560-573. DOI: 10.1109/JSSC.2011.2170778.
[FPT]
Y.-C. Chen, W. Wang, W. Zhang, and H. Li, “uBRAM-based Run-time Reconfigurable FPGA and Corresponding Reconfiguration Methodology,” International Conference on Field-Programmable Technology (FPT), Dec. 2012, pp. 80-86. DOI: 10.1109/FPT.2012.6412116.
[ICCAD]
X. Bi, Z. Sun, H. Li, and W. Wu, “Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches,” International Conference on Computer Aided Design (ICCAD), Nov. 2012, pp. 88-94. DOI: 10.1145/2429384.2429401. (Best Paper Nomination)
[ICCAD]
Y. Zhang, L. Zhang, W. Wen, G. Sun and Y. Chen, “Multi-level Cell STT-RAM: Is It Realistic or Just a Dream?” International Conference on Computer Aided Design (ICCAD), Nov. 2012, pp.526-532. DOI: 10.1145/2429384.2429498.
[ISVLSI]
Z. Shao, Y. Liu, Y. Chen, and T. Li, “Utilizing PCM for Energy and Power Optimization in Embedded Systems,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Aug. 2012, pp. 398-403. DOI: 10.1109/ISVLSI.2012.81. (Invited)
[ISVLSI]
X. Bi, H. Li, and J.-J. Kim, “Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Aug. 2012, pp. 374-379. DOI: 10.1109/ISVLSI.2012.56. (Invited)
[FPL]
Y.-C. Chen, W. Zhang, and H. Li, “Non-volatile 3D stacking RRAM-based FPGA,” International Conference on Field Programmable Logic and Applications (FPL), Aug. 2012, pp. 367-372. DOI: 10.1109/FPL.2012.6339206.
[ISLPED]
Z. Sun, H. Li, and W. Wu, “A Dual-mode Architecture for Fast-switching STT-RAM,” International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2012, pp. 45-50. DOI: 10.1145/2333660.2333673.
[ISLPED]
Z. Sun, X. Bi, and H. Li, “Process Variation Aware Data Management for STT-RAM Cache Design,” International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2012, pp. 179-184. DOI: 10.1145/2333660.2333706.
[DAC]
W. Wen, Y. Zhang, Y. Chen, Y. Wang, and Y. Xie, “PS3-RAM: A Fast, Portable and Scalable Statistical STT-RAM Reliability Analysis Method,” Design Automation Conference (DAC), Jun. 2012, pp. 1191-1196. DOI: 10.1145/2228360.2228580.
[ISCAS]
Y.-C. Chen, H. Li, and W. Zhang, “A Novel Peripheral Circuit for RRAM-based LUT,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2012, pp. 1811-1814. DOI: 10.1109/ISCAS.2012.6271619.
[DATE]
Y. Zhang, X. Wang, Y. Li, A. Jones and Y. Chen, “Asymmetry of MTJ Switching and Its Implication to the STT-RAM Designs,” Design, Automation & Test in Europe (DATE), Mar. 2012, pp. 1313-1318. DOI: 10.1109/DATE.2012.6176695.
[ASPDAC]
Y. Chen, Y. Zhang and P. Wang, “Probabilistic Design in Spintronic Memory and Logic Circuit,” Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2012, 323-328. DOI: 10.1109/ ASPDAC.2012.6164967. (Invited)
[ASPDAC]
Y.-C. Chen, W. Zhang, and H. Li, “A Look Up Table Design with 3D Bipolar RRAMs,” the 17th Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2012, pp. 73-78. DOI: 10.1109/ASPDAC.2012.6165051.
[2011]
[CRC]
H. Li, and Y. Chen, Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing, CRC Press, Dec. 19, 2011. ISBN: 978-14-398-0745-3.
[TMAG]
P. Wang, X. Wang, Y. Zhang, H. Li, S.P. Levitan, and Y. Chen, “Nonpersistent Error Optimization in Spin-MOS Logic and Storage Circuitry,” IEEE Transaction on Magnetics (TMAG), vol. 47, no.10, Oct. 2011, pp. 3860-3863. DOI: 10.1109/TMAG.2011.2153838.
[TMAG]
Y. Zhang, X. Wang, H. Li, and Y. Chen, “STT-RAM Cell Optimization Considering MTJ and CMOS Variations,” IEEE Transaction on Magnetics (TMAG), vol. 47, no.10, Oct. 2011, pp. 2962-2965. DOI: 10.1109/TMAG.2011.2158810.
[TMAG]
H. Li, X. Wang, Z.-L. Ong, W.-F. Wong, Y. Zhang, P. Wang and Y. Chen, “Performance, Power and Reliability Tradeoffs of STT-RAM Cell Subject to Architecture-level Requirement,” IEEE Transaction on Magnetics (TMAG), vol. 47, no.10, Oct. 2011, pp. 2356-2359. DOI: 10.1109/TMAG.2011.2159262.
[MICRO]
Z. Sun, X. Bi, H. Li, W.-F. Wong, Z.-L. Ong, X. Zhu and W. Wu, “Multi Retention Level STT-RAM Cache Designs,” International Symposium on Microarchitecture (MICRO), Dec. 2011, pp. 329-338. (DOI: 10.1145/2155620.2155659)
[CODES+ISSS]
J. Xue, Y. Zhang, Y. Chen, G. Sun, J. J. Yang, and H. Li, “Emerging Non-Volatile Memories: Opportunities and Challenges,” International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct. 2011, pp.325-334. DOI: 10.1145/2039370.2039420. (Invited)
[ICCAD]
Y. Zhang, X. Wang and Y. Chen, “STT-RAM Cell Design Optimization for Persistent and Non-Persistent Error Rate Reduction: A Statistical Design View,” International Conference on Computer Aided Design (ICCAD), Nov. 2011, pp. 471-477. DOI: 10.1109/ICCAD.2011.6105370.
[CICC]
P. Wang, X. Chen, Y. Chen, H. Li, S. Kang, X. Zhu, and W. Wu, “A 1.0V 45nm Nonvolatile Magnetic Latch Design and Its Robustness Analysis,” IEEE Custom Integrated Circuits Conference (CICC), Sep. 2011, pp.1-4. DOI: 10.1109/CICC.2011.6055392.
[NVMW-wkp]
Y. Chen, X. Wang, W.-F. Wong, H. Li, “Performance, Power and Reliability Tradeoffs of STT-RAM Cell Subjective to Architecture-level Requirement,” The Non-Volatile Memories Workshop, Mar. 2011. (Poster).
[InterMag-talk]
H. Li, X. Wang, Z.-L. Ong, W.-F. Wong, Y. Zhang, P. Wang and Y. Chen, “Performance, Power and Reliability Tradeoffs of STT-RAM Cell Subjective to Architecture-level Requirement,” IEEE International Magnetics Conference (InterMag), Apr. 2011, AD-02.