The objective of the research is to develop design technologies that can alleviate the general robustness issues of the next-generation nonvolatile memories while maintaining and even improving the generic memory specifications such as density, power and performance. Comprehensive solutions are integrated from architecture, circuit and device layers for the improvement on the density, cost and reliability of emerging nonvolatile memories.
The design techniques include 1) a new write endurance improvement technique for multi-level cell devices to prolong the lifetime of the new nonvolatile memories by applying the coding and wear-leveling techniques that are monitored and controlled by self-contained circuits; 2) self-reference and other adaptive sensing techniques to overcome the impacts of process variations and device wear-out mechanisms for yield improvement.; and 3) a new interleaved 3D-stacking memory integration scheme and peripheral circuit design to increase the number of stacks integrated within a certain height.
The broader impact of the research lies in revealing the importance of applying cross-layer design techniques to resolve the robustness issues of the next-generation NVMs and the attentions to the robust design context. The system architects, the circuit designers and the device integration engineers can be well bridged and educated by the research innovations. The developed techniques can be directly transferred to industry applications under the close collaborations with several industry partners, and directly impact the future computing systems.
|Senior Personnel:||Prof. Hai (Helen) Li (PI) and Prof. Yiran Chen (PI)|
|Sponsors:||National Science Foundation (Prof. Li’s Award)
National Science Foundation (Prof. Chen’s Award)
|Team Members:||Xiuyuan Bi, Yi-Chung Chen, Sicheng Li, Chenchen Liu, Mengjie Mao, Zhenyu Sun, Peiyuan Wang, Wujie Wen, and Yaojun Zhang|
|Collaborators:|| Dr. Rajiv Joshi, IBM T. J. Watson Research Center
Prof. Guangyu Sun, Peking University
Dr. Xiaobin Wang, Avalanche Technology
Y. Zhang, Y. Li, Z. Sun, H. Li, Y. Chen, and Alex K. Jones, “Read Performance: The Newest Barrier in Scaled STT-RAM,” IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, to appear. DOI: 10.1109/TVLSI.2014.2326797.