The objective of the research is to develop an innovative spin-transfer torque random access memory (STT-RAM) based memory hierarchy to meet the demands of modern embedded systems for low-power, fast-speed and high-density on-chip data storage.
Three integrated components are included in our research to address the major technical concerns in STT-RAM designs: (1) Application-driven STT-RAM cell design and optimization to target different embedded system specifications. (2) Thermal resilient adaptive STT-RAM memory hierarchy to tolerate the temperature instability of STT-RAM incurred by ambient temperature and self-heating. (3) Probabilistic STT-RAM design methodology to improve the run-time stability and/or the performance.
This research provides a comprehensive design package for efficiently integrating STT-RAM into modern embedded system designs and offers unparalleled performance and power advantages. The system architects and the circuit designers can be well bridged and educated by the research innovations. The developed techniques can be directly transferred to industry applications under the close collaborations with several industry partners, and directly impact the future embedded systems. The activities in the collaboration also include the tutorials in the major conferences on the technical aspects of the projects and new course development.
| Senior Personnel: | Prof. Hai (Helen) Li (PI) |
| Sponsors: | National Science Foundation |
| Team Members: | Xiuyuan Bi, Enes Eken, Mengjie Mao, and Zhenyu Sun |
| Collaborators: | Dr. Wenqing Wu, Qualcomm Inc. Prof. Weng-Fai Wong, National University of Singapore |
| Starting Date: | 09/01/2012 |
Related Publications:
[In Press]
[TMAG]
E. Eken, Y. Zhang, W. Wen, R. Joshi, H. Li, and Y. Chen, “A Novel Self-reference Technique for STT-RAM Read and Write Reliability Enhancement,” IEEE Transaction on Magnetics (TMAG), to appear.
[2014]
[Springer]
Y. Chen, H. Li and Z. Sun, Spintronic Memristor as Interface between DNA and Solid State Devices, (in Memristors and Memristive Systems, Editor: Ronald Tetzlaff), Springer, Jan. 1, 2014. ISBN: 978-1-4614-9067-8.
[TVLSI]
Z. Sun, X. Bi, H. Li, W.-F. Wong, and X. Zhu, “STT-RAM Cache Hierarchy with Multi-retention MTJ Designs,” IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol. 22, no. 6, Jun. 2014, pp. 1281-1293. DOI: 10.1109/TVLSI.2013.2267754
[ASPDAC]
J. Wang, Y. Tim, W.-F. Wong, Z.-L. Ong, Z. Sun, and H. Li, “A Coherent Hybrid SRAM and STT-RAM L1 Cache Architecture for Shared Memory Multicores,” Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2014, pp. 610-615. (DOI: 10.1109/ASPDAC.2014. 6742958)
[DAC]
E. Eken, Y. Zhang, W. Wen, R. Joshi, H. Li, and Y. Chen, “A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability,” Design Automation Conference (DAC), Jun. 2014, pp. 1-6. DOI: 10.1145/2593069.2593075.
[DAC]
M. Mao, W. Wen, Y. Zhang, H. Li, and Y. Chen, “Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory,” Design Automation Conference (DAC), Jun. 2014, pp. 1-6. DOI: 10.1145/2593069.2593137.
[DATE-WIP]
E. Park, S. Yoo, S. Lee, and H. Li, “Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation,” Design, Automation & Test in Europe (DATE), Mar. 2014, pp. 1-4. (DOI: 10.7873/DATE2014.172)
[InterMag-talk]
E. Eken, Y. Zhang, W. Wen, R. Joshi, H. Li, and Y. Chen, “A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability,” IEEE International Magnetics Conference (InterMag), May 2014, CC-09.
[2013]
[Springer]
H. Li, Z. Sun, X. Bi, W.-F. Wong, X. Zhu, and W. Wu, “STT-RAM Cache Hierarchy Design and Exploration with Emerging Magnetic Devices,” (in Emerging Memory Technologies − Design, Architecture, and Applicants, Editor: Yuan Xie), Springer, Aug. 31, 2013. ISBN: 978-1-4419-9550-6.
[TACO]
Y. Li, Y. Zhang, H. Li, Y. Chen, and A. Jones, “C1C: A Configurable, Compiler-guided STT-RAM L1 Cache,” European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC) also ACM Transactions on Architecture and Code Optimization (TACO), vol. 10, no. 4, article 52, Dec. 2013. DOI: 10.1145/2541228.2555308.
[TODAES]
B. Zhao, J. Yang, Y. Zhang, Y. Chen and H. Li, “Common-Source-Line Array: An Area Efficient Memory Architecture for Bipolar Nonvolatile Devices,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 18, no. 4, article 57, Oct. 2013. DOI: 10.1145/2500459.
[JETC]
Y. Chen, W. Wong, H. Li, C.-K. Koh, *Y. Zhang, and *W. Wen, “On-chip Caches built on Multi-Level Spin-Transfer Torque RAM Cells and Its Optimizations,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 9, no 2, article 16, May 2013. DOI: 10.1145/2463585.2463592.
[ICCAD]
Y. Zhang, I. Bayram, Y. Wang, H. Li, and Y. Chen, “ADAMS: Asymmetric Differential STT-RAM Cell Structure for Reliable and High-performance Applications,” International Conference on Computer Aided Design (ICCAD), Nov. 2013, pp. 9-16. DOI: 10.1109/ICCAD.2013.6691091.
[ICCAD]
X. Bi, M. Mao, D. Wang, and H. Li, “Unleashing the Potential of MLC STT-RAM Caches,” International Conference on Computer-Aided Design (ICCAD), Nov. 2013, pp. 429-436. DOI: 10.1109/ICCAD.2013.6691153. (Best Paper Nomination)
[DAC]
Z. Sun, W. Wu, and H. Li, “Cross-Layer Racetrack Memory Design for Ultra High Density and Low Power Consumption,” Design Automation Conference (DAC), Jun. 2013, Article 53. DOI: 10.1145/2463209.2488799.
[GLSVLSI]
M. Mao, H. Li, A. Jones, and Y. Chen, “Coordinating Prefetching and STT-RAM-based Last-level Cache Management for Multicore Systems,” Great Lakes Symposium on VLSI (GLVLSI), May 2013, pp. 55-60. DOI: 10.1145/2483028.2483060. (Best Paper Award)
[DATE]
X. Bi, A. M. Weldon, and H. Li, “STT-RAM Designs Supporting Dual-port Accesses,” Design, Automation & Test in Europe (DATE), Mar. 2013, pp. 853-858. DOI: 10.7873/DATE.2013.180.
[DAAMC-wkp]
Y. Zhang, *I. Bayram, Y. Wang, H. Li and Y. Chen, “ADAMS: Asymmetric Differential STT-RAM Cell Structure for Reliable and High-performance Applications,” International Workshop on Design Automation for Analog and Mixed-Signal Circuits, Nov. 2013. (Poster)
[2012]
[TVLSI]
Z. Sun, H. Li, Y. Chen, and X. Wang, “Voltage Driven Non-Destructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory,” IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol. 20, no. 11, Nov. 2012, pp. 2020-2030. DOI: 10.1109/TVLSI.2011.2166282.
[TMAG]
X. Bi, H. Li, and X. Wang, “STT-RAM Cell Design Considering CMOS and MTJ Temperature Dependence,” IEEE Transaction on Magnetics (TMAG), vol. 48, no. 11, Nov. 2012, pp. 3821-3824. DOI: 10.1109/TMAG.2012.2200469.
[SPIN]
H. Li and Z. Sun, “Voltage Driven Non-destructive Self-reference Sensing for STT-RAM Yield Enhancement,” SPIN, vol. 2, no. 3, Sep. 2012, (124008). DOI: 10.1142/S2010324712400085.
[JETC]
Z. Sun, X. Chen, Y. Zhang, H. Li and Y. Chen, “Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 8, no. 2, article 13, Jun. 2012. DOI: 10.1145/2180878.2180885.
[JAP]
Z. Sun, H. Li, and X. Wang, “MTJ Design Margin Exploration for Self-Reference Sensing,” Journal of Applied Physics (JAP), vol. 111, Mar. 2012, (07C726). DOI: 10.1063/1.3679647.
[ICCAD]
X. Bi, Z. Sun, H. Li, and W. Wu, “Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches,” International Conference on Computer Aided Design (ICCAD), Nov. 2012, pp. 88-94. DOI: 10.1145/2429384.2429401. (Best Paper Nomination)
[ISVLSI]
X. Bi, H. Li, and J.-J. Kim, “Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Aug. 2012, pp. 374-379. DOI: 10.1109/ISVLSI.2012.56. (Invited)
[ISLPED]
Z. Sun, H. Li, and W. Wu, “A Dual-mode Architecture for Fast-switching STT-RAM,” International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2012, pp. 45-50. DOI: 10.1145/2333660.2333673.
http://dl.acm.org/citation.cfm?id=2333673
[ISLPED]
Z. Sun, X. Bi, and H. Li, “Process Variation Aware Data Management for STT-RAM Cache Design,” International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2012, pp. 179-184. DOI: 10.1145/2333660.2333706.
[DATE-WIP]
B. Zhao, J. Yang, Y. Zhang, Y. Chen and H. Li, “Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices,” Design, Automation & Test in Europe (DATE), Mar. 2012, pp. 1451-1454. DOI: 10.1109/DATE.2012.6176594.