Zhenyu Sun’s paper entitled “STT-RAM Cache Hierarchy with Multi-retention MTJ Designs” is published on June issue of IEEE Transactions on Very Large Scale Integration (TVLSI) Systems. (Co-authors: Z. Sun, *X. Bi, H. Li, W.-F. Wong, and X. Zhu)

Link: http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6553181&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D6553181