The major technical obstacles for the adoption of STT-RAM are the high write power consumption and long write access time. When write access of a STT-RAM cell operates at sub-10ns region, the required switching current increases exponentially as the MTJ switching time decreases. The attempt to improve the STT-RAM write performance by raising the switching current inevitably leads to the increase in the driving transistor size, imposes significant cell area overheads, and degrades the memory cell reliability. 10-nanosecond MTJ switching time is widely believed as the performance limitations of STT-RAM technology and adopted as the design specifications in mainstream research and development efforts.
Our research project proposes to break the long-believed 10ns write performance wall of STT-RAM technology through a cross-layer solution from architecture, circuit and device levels. Based on the fact that the data in the memory hierarchy of modern computing systems are frequently updated or replaced, we plan to trade the data retention time of STT-RAM cells for the improvement on the memory write access time and power consumption. A statistical design flow that takes into account the CMOS and MTJ device variations as well as the thermal fluctuations during MTJ switching is also proposed for the design optimization of the STT-RAM cells working in sub-10ns region.
| Senior Personnel: | Prof. Yiran Chen (PI) |
| Sponsors: | University of Pittsburgh |
| Team Members: | Wujie Wen |
| Collaborators: | N/A |
| Performance Date: | 07/01/2011 – 06/30/2013 |
Related Publications:
[In Press]
[2014]
[2013]
[2012]