Memristor-Based Computing Architecture: Design Methodologies & Circuit Techniques

The unique properties of a memristor make it promising in neuromorphic computing systems: First, the prototyped memristor devices have demonstrated the scalability down to 10 nm and below. Accordingly, the memristor memories can achieve a high integration density of 100Gbits/cm2, a few times higher than the flash memory technologies. Second, the memristor device has an intrinsic and remarkable feature called “pinched hysteresis loop”, which means it can “remember” the total electric charge flowing through it. Consequently, the memristor-based memories with both the high-integration capability and the pinched hysteresis characteristic can be applied to a massively-parallel, large-scale neuromorphic computing processor architecture.

In this project, we investigated memristor-based reconfigurable design techniques. The structure is built upon single memristor-based synapse and the corresponding training circuit design. The design optimization and its implementation in multi-synapse systems are also analyzed. With the aid of sharing training circuit and self-training mode, the performance and energy can be significantly improved. The proposed techniques can potentially be extended to develop a neuromorphic computing processor architecture.

 

Senior Personnel: Prof. Hai (Helen) Li (PI)
Sponsors: US Air Force Research Lab
Team Members: Miao Hu and Hui Wang
Collaborators: Dr. Qing Wu, U.S. Air Force Research Lab
Performance Date: 10/01/2010 – 09/30/2012

 

Related Publications:

[2012]

[Springer]

H. Li and R. E. Pino, “Statistical Memristor Model and Its Applications in Neuromorphic Computing,” (in Advances in Neuromorphic Memristor Science and Applications, Editor: R. Kozma, R. E. Pino, and G. Pazienza), Springer, Jun. 28, 2012. ISBN: 978-94-007-4490-5.

[TNANO]
Y.-C. Chen, H. Li, W. Zhang and R. Pino, “The 3D Stacking Bipolar RRAM for High Density,” IEEE Transaction on Nanotechnology (TNANO), vol. 11, no. 5, Sep. 2012, pp. 948-956. (DOI: 10.1109/TNANO.2012.2208759)

[IJCNN]
H. Wang, H. Li, and R. E. Pino, “Memristor-based Synapse Design and Training Scheme for Neuromorphic Computing Architecture,” International Joint Conference on Neural Networks (IJCNN), Jun. 2012, pp. 1-5. DOI: 10.1109/IJCNN.2012.6252577.

[DAC]
R. Pino, H. Li, Y. Chen, M. Hu and B. Liu, “Statistical Memristor Modeling and Case Study in Neuromorphic Computing,” Design Automation Conference (DAC), Jun. 2012, pp. 585-590. DOI: 10.1145/2228360.2228466. (Invited)

[DATE]
X. Bi, H. Li, Y. Chen, and R. Pino, “Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference,” Design, Automation & Test in Europe (DATE), Mar. 2012, pp. 1301-1306. DOI: 10.1109/DATE.2012.6176693.

 

[2011]

[NANOARCH]
Y.-C. Chen, H. Li, W. Zhang and R. Pino, “3D-HIM: A 3-Dimensional High-Density Interleaved Memory for Bipolar RRAM Design,” International Symposium on Nanoscale Architectures (NANOARCH), Jun. 2011, pp. 59-64. (DOI: 10.1109/NANOARCH.2011.5941484)

[DATE-WIP]
Y.-C. Chen, H. Li, Y. Chen and R. Pino, “3D-ICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory,” Design, Automation & Test in Europe (DATE), Mar. 2011, pp. 1-4. DOI: 10.1109/DATE.2011.5763289.

[ASPDAC]
M. Hu, H. Li, Y. Chen, X. Wang, and R. E. Pino, “Geometry Variations Analysis of TiO2–based and Spintronic Memristors,” 16th Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2011, pp. 25-30. DOI: 10.1109/ASPDAC.2011.5722193. (Best Paper Nomination)

[DAC-WIP]
M. Hu, H. Li, Y. Chen, and R. E. Pino, “Statistical Model of TiO2 Memristor,” Design Automation Conference (DAC), Jun. 2011.