SHF: Small: Collaborative Research: STEMS: STatistic Emerging Memory Simulator

Emerging memory technologies such as Magnetoresistive random-access memory (MRAM), Phase-change memory (PCRAM), and Resistive random-access memory (RRAM) are being explored as potential alternatives for future computing systems. However, traditional memory design methodologies are not sufficient to address probabilistic behaviors, which are caused by process variations and the intrinsic randomness in the physical mechanisms (e.g., thermal fluctuations) of these emerging technologies.

The objective of this research is to develop a design methodology called STatistical Emerging Memory Simulator (STEMS) for circuit/architecture designs with such emerging memory technologies. The intellectual merits include the following: (1) developing a generic statistical characterization formalism to link the emerging memory cell design specifications with design variables, process variations and environmental fluctuations, (2) deriving a variation-aware compact memory cell model to fulfill the demands of the statistical design optimizations at cell and array levels, and (3) investigating a statistical memory design methodology to explore the tradeoffs among memory structure, implementation cost, and design specifications for various system requirements. The proposed research will fundamentally change the design methodologies for future memory technologies, initiate an innovative direction in memory designs, and optimize and balance the new design characteristics of emerging memories under architectural considerations, inspiring the transition of design philosophy from the deterministic era to the probabilistic era. The proposed techniques provide a complementary perspective to the existing probabilistic system and architectural research while emphasizing the yield and probabilistic properties of memory designs.

This project will facilitate further advances and wider adoption of the emerging memory technologies by the semiconductor industry. Innovations in design methods and memory modeling will have an impact on the way in which semiconductor memory chips are designed and fabricated.

 

Senior Personnel: Prof. Yiran Chen (PI)
Sponsors: National Science Foundation
Team Members: Jie Guo, Xiaoxiao Liu, Peiyuan Wang, Wujie Wen, and Yaojun Zhang
Collaborators: Dr. Rajiv Joshi, IBM T. J. Watson Research Center
Prof. Guangyu Sun, Peking University

Prof. Danghui Wang, Northwestern Polytechnic University

Prof. Weng-Fai Wong, National University of Singapore

Prof. Wei Zhang, The Hong Kong University of Science and Technology

 Starting Date: 07/01/2012

Related Publications:

[In Press]

[TCAD]
W. Wen, Y. Zhang, Y. Wang, Y. Chen, and Y. Xie, “PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method,” IEEE Transactions on CAD of Integrated Circuits and Systems (TCAD), to appear.

[2014]

[ISCE]
W. Wen, Y. Zhang, M. Mao, and Y. Chen, “STT-RAM Reliability Enhancement through ECC and Access Scheme Optimization,” International Symposium on Consumer Electronics (ISCE), Jun. 2014, pp. 22-25. DOI: 10.1109/ISCE.2014.6884324. (Invited)download-icon

[DAC]
W. Wen, M. Mao, Y. Zhang, and Y. Chen, “State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System,” Design Automation Conference (DAC), Jun. 2014, pp. 1-6. DOI: 10.1145/2593069.2593220. (Best Paper Nomination)download-icon

[ASPDAC]
X. Liu, Y. Li, Y. Zhang, A. Jones, and Y. Chen, “STD-TLB: A STT-RAM-based Dynamically-configurable Translation Lookaside Buffer for GPU Architectures,” Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2014, pp. 355-360. DOI: 10.1109/ASPDAC.2014.6742915.download-icon

 

[2013]

[JETC]
Y. Chen, W. Wong, H. Li, C.-K. Koh, *Y. Zhang, and *W. Wen, “On-chip Caches built on Multi-Level Spin-Transfer Torque RAM Cells and Its Optimizations,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 9, no 2, article 16, May 2013. DOI: 10.1145/2463585.2463592.download-icon

[ICCAD]
W. Wen, M. Mao, S. Kang, X. Zhu, D. Wang and Y. Chen, “CD-ECC: Content-Dependent Error Correction Codes for Combating Asymmetric Nonvolatile Memory Operation Errors,” International Conference on Computer Aided Design (ICCAD), Nov. 2013, pp. 1-8. DOI: 10.1109/ICCAD.2013.6691090.download-icon

[DATE]
J. Guo, W. Wen, and Y. Chen, “DA-RAID-5: A Disturb Aware Data Protection Technique for NAND Flash Storage Systems,” Design, Automation & Test in Europe (DATE), Mar. 2013, pp. 380-385. DOI: 10. 7873/DATE.2013.087.download-icon

[DATE]
J. Guo, J. Yang, Y. Zhang and Y. Chen, “Low Cost Power Failure Protection for MLC NAND Flash Storage Systems with PRAM/DRAM Hybrid Buffer,” Design, Automation & Test in Europe (DATE), Mar. 2013, pp. 859-864. DOI: 10.7873/DATE.2013.181.download-icon

 

 

[2012]

[JETC]
Y. Chen, W. Wong, H. Li, C.-K. Koh, Y. Zhang, and W. Wen, “On-chip Caches built on Multi-Level Spin-Transfer Torque RAM Cells and Its Optimizations,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 9, no 2, article 16, May 2013. DOI: 10.1145/2463585.2463592.download-icon

 

[SPIN]
Y. Zhang, W. Wen, and Y. Chen, “STT-RAM Cell Design Considering MTJ Asymmetric Switching,” SPIN, vol. 2, no. 3, Nov. 2012, (1240007). DOI: 10.1142/S2010324712400073.download-icon

 

[ICCAD]
Y. Zhang, L. Zhang, W. Wen, G. Sun and Y. Chen, “Multi-level Cell STT-RAM: Is It Realistic or Just a Dream?” International Conference on Computer Aided Design (ICCAD), Nov. 2012, pp.526-532. DOI: 10.1145/2429384.2429498.download-icon

 

[ICCAD]
P. Wang, W. Zhang, R. Joshi, R. Kanj and Y. Chen, “A Thermal and Process Variation Aware MTJ Switching Model and Its Applications in Soft Error Analysis,” International Conference on Computer Aided Design (ICCAD), Nov. 2012, pp.720-727. DOI: 10.1145/2429384.2429541.download-icon