The explosion of “big data” applications imposes severe challenges of data processing speed and scalability on traditional computer systems. However, the performance of von Neumann machine is greatly hindered by the increasing performance gap between CPU and memory (“known as memory wall”), motivating the active research on new or alternative computing architecture. As one important instance, neuromorphic computing systems have gained considerable attentions. Neuromorphic computing systems refer to the computing architecture inspired by the working mechanism of human brains. The human neocortex system naturally possesses a massively parallel architecture with closely coupled memory and computing units as well as the unique analog domain operations. By imitating such structure, neuromorphic computing system is anticipated to be superior to the conventional computer systems in cognitive applications like image recognition and natural language understanding. Among all the possible solutions, cortical processor has gained significant attention. The cortical-like hierarchical model conducts data processing by using spatial and temporal evolution of the data representation to form relationships. The straightforward hardware realization of such massively parallel algorithms inspired by cortical models, however, commonly consumes a large volume of memory and computing resources, incurring high design complexity and hardware cost.
We suggest realizing the brain-inspired computing architecture by combining the flexibility of conventional architecture in computation and the efficiency of the emerging memristor technology. In particular, we proposed to use resistive crossbar to speed-up common neuromorphic algorithms, e.g., mapping matrix-vector multiplications to memristor array. In this project, we plan to design and simulation all the critical circuit components that enable a comprehensive memristor crossbar based neuromorphic computing engine. Two types of hardware implementations, i.e., the level-based design for high execution performance and the spike-based version for extremely high energy efficiency, will be examined and compared. The target application of the chip design is character recognition, which may be first implemented as hard-coded in CMOS-only.
|Senior Personnel:||Prof. Hai (Helen) Li (PI), Prof. Yiran Chen (co-PI), and Prof. Z.-H. Mao (senior personnel)|
|Sponsors:||US Air Force Research Lab|
|Team Members:||Xiaoxiao Liu, Chaofei Yang, and Zheng Li|
|Collaborators:||Prof. Hao Jiang, San Francisco State University
Dr. Jianhua Yang, HP Labs
Related Publications: N/A