Memristor Crossbar Based Neuromorphic Hardware Systems

Because of the continuously increased gap between the CPU computing power and the memory bandwidth, traditional Von Neumann computer architecture becomes less and less efficient to handle the exascale computation tasks. In the last decades, neuromorphic computing systems, which can potentially offer the capabilities of biological perception and information processing atop a high-density, powerful and energy-efficient platform, have gained great attentions from computing society. However, these research activities have been narrowly carried out on neural network algorithm enhancement and/or system implementations built upon the conventional computing units, i.e., CPU, GPU, or FPGA etc. Very recently, a new type of device called memristors is discovered by HP Labs as the 4th fundamental circuit element. Memristors have a unique capability to remember the historical profiles of the excitations and record the history as their analogous states. The similarity of memristor-based circuit to biological synaptic behavior made a ground-breaking breakthrough on the design of the corresponding neuromorphic hardware systems and encouraged a lot of research on this area.

Different from the previous works focusing on mimicking the synaptic behaviors by using CMOS circuit design with one or a few memristor devices, in this project, we propose to construct a memristor crossbar array as a generic hardware engine for neuromorphic computing. Specifically, we will investigate the hardware realization of neural network algorithm on top of memristor crossbar arrays for higher computation efficiency and lower hardware resource requirement. We then propose a Brain-State-in-a-Box (BSB) circuit based on the memristor crossbar arrays for optical character recognition (OCR) applications. The impacts of realistic parameters on the robustness of the BSB circuits, such as input defects, process variations, and electrical fluctuations, will be evaluated based on massive Monte-Carlo simulations. The physical constraints for the implementations of the proposed neural network on memristor crossbar arrays will be also discussed. The established memristor array design and its peripheral circuit offer a generic hardware engine for neuromorphic algorithm development and realization and accelerate the adoption of the bio-inspired computing platform in emerging applications.


Senior Personnel: Prof. Yiran Chen (PI)
Sponsors: HP Labs
Team Members: Miao Hu, Beiye Liu, and Lu Zhang
Collaborators: N/A
 Starting Date: 09/01/2012

Related Publications:

[In Press]


I. Bayram and Y. Chen, “NV-TCAM: Alternative Interests and Practices in NVM Designs,” IEEE Non-Volatile Memory Systems and Applications Symposium (NVMSA), Aug. 2014, to appear. (Invited)


L. Zhang, Z. Chen, J. J. Yang, B. Wysocki, N. McDonald and Y. Chen, “A Compact Modeling of TiO2-TiO2-x Memristor,”  Applied Physics Letters (APL), vol. 102, no. 15, 153503 (2013). DOI: 10.1063/