ECC Designs for High-Performance High-Reliable STT-MRAM

The demand of modern computer systems on the capacity of main memory grows sharply due to their exponentially increased data processing capability. However, the technology scaling of conventional DRAM technique is facing severe challenges in dynamic and leakage power consumption control as well as the significantly degraded device reliability. As one of the promising technique to replace DRAM, spin-transfer torque random access memory (STT-RAM) recently received the increasing attentions. By storing the information as the resistance states of a magnetic tunneling junction (MTJ) device, STT-RAM coffers the fast access time comparable to SRAM, the high integration density close to DRAM, the non-volatility of Flash, and good scalability, etc. However, many technical obstacles still need to be overcome before seamlessly integrating STT-RAM into off-chip memory designs. Some examples include the long write latency and high write energy, the temperature instability, and the non-persistent write failures induced by the thermal fluctuations. In particular, the extremely asymmetric write errors of STT-MRAM at the bit-flipping’s of 0→1 and 1→0, which cannot be efficiently repaired by conventional ECC or redundancy schemes, poses a serious concern in STT-RAM designs.

The goal of our proposed research is to develop the novel ECC scheme for high-reliable and high-performance STT-RAM to meet the requirements of low-power, fast-speed and high-density off-chip data storage. In this project, we will investigate an asymmetric write channel (AWC) model of STT-RAM to evaluate the write error rate and design high-efficiency ECCs by leveraging the understanding on the inherent stochastic MTJ switching process and new ECC design concept. Both ECCs for SLC and MLC STT-MRAM designs will be explored. The success of the project will lead to a new STT-RAM-based memory hierarchy design with significantly improved robustness, access performance and power consumption, accelerating the adoption of STT-RAM in the modern off-chip memory designs.

 

Senior Personnel: Prof. Yiran Chen (PI)
Sponsors: Samsung
Team Members: Wujie Wen and Bonan Yan
Collaborators:  N/A
 Starting Date: 02/01/2013

Related Publications:

[TCAD]
W. Wen, Y. Zhang, Y. Wang, Y. Chen, and Y. Xie, “PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method,” IEEE Transactions on CAD of Integrated Circuits and Systems (TCAD), to appear.

[ISCE]
W. Wen, Y. Zhang, M. Mao, and Y. Chen, “STT-RAM Reliability Enhancement through ECC and Access Scheme Optimization,” International Symposium on Consumer Electronics (ISCE), Jun. 2014, pp. 22-25. DOI: 10.1109/ISCE.2014.6884324. (Invited)download-icon

[DAC]
W. Wen, M. Mao, Y. Zhang, and Y. Chen, “State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System,” Design Automation Conference (DAC), Jun. 2014, pp. 1-6. DOI: 10.1145/2593069.2593220. (Best Paper Nomination)

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