Design for Manufacturing Method for Memristor-based Neuromorphic Computing Processors

As the 4th fundamental passive circuit element, memristor has recently received increasing attentions since the first real device was reported by HP Lab in 2008. A memristor can record the historic profile of the voltage/current through itself and store the corresponding state permanently. The combined memory and learning capabilities of memristors create great potentials in various system designs, for instance, Neuromorphic computing platforms. However, before a very large scale circuit can be implemented, there are many fundamental technical obstacles need to be overcome.

The memristor-inspired reconfigurable Neuromorphic computing chip recently draws increasing attentions in computational intelligence community. To ensure the success of the manufacturing of a reconfigurable Neuromorphic computing chip, a thorough design and planning of chip layout and testing must be made. The main objective of this project is to develop and plan a robust chip tape-out for a reconfigurable Neuromorphic computing chip design. Our proposed research include the following tasks: (1) We shall implement the robust layout design for reconfigurable Neuromorphic computing chip; (2) We shall develop the comprehensive E-test modules to debug the chip design and the integration process etc.; and 3) We shall propose the corresponding testing plan to validate our reconfigurable Neuromorphic computing chip design. The proposed techniques will be used to build a real reconfigurable Neuromorphic computing chip by collaborating with the circuit design team working on the same chip design project.

The key transformative aspect of the proposed research is that, the success of the project will result in the innovations in reconfigurable Neuromorphic computing chip design, accelerating commercialization of Neuromorphic computing technologies, and potentially leading to better performance, higher energy-efficient, and more robust chip manufacturing.


Senior Personnel: Prof. Yiran Chen (PI)
Sponsors: US Air Force Research Lab
Team Members: Beiye Liu
Collaborators: N/A
Performance Date: 10/01/2011 – 09/30/2012

Related Publications:



B. Liu, Y. Chen, B. Wysocki, and T. Huang, “Reconfigurable Neuromorphic Computing System with Memristor-Based Synapse Design,” Neural Processing Letters (NPL), Aug. 2013, pp. 1-9. DOI: 10.1007/