An Adaptive Information Processing System Resilient to Device Variations and Noises

The aggressive technology scaling imposes severe reliability challenges on present-day VLSI designs, e.g., the probabilistic behaviors of nano-scale circuitry due to process variations. Logic gates and memory cells also turn to be highly vulnerable to radiation-induced soft-errors due to the limited electrical charge stored on the internal capacitance. In this project, we propose a comprehensive solution set combating the statistical properties and intermittent failures incurred by the technology scaling in computing systems. In contrast to many existing approaches that focus on circuit and structural enhancements, our proposal offers an adaptive information processing VLSI system with significant revolutions across the levels of device, circuit, architecture and algorithm. The design starts with the adoption of emerging memristor technology which is intrinsically resilient to soft errors and friendly to technology scaling. A robust computing engine built on high-density memristor crossbar array with CMOS/memristor hybrid mixed-signal peripheral circuitry is then proposed for intensive computations. Novel computation algorithms with online programming and noise filtering will be developed to accommodate the stochastic behaviors of memristors incurred by process variations and environmental fluctuations, offering high computation parallelism, high power efficiency and high system reliability. The proposed design aims at a broad spectrum of military applications with rich matrix operations and learning process. A successful application example inspired by our collaboration with AFRL – document image processing, is presented.

 

Senior Personnel: Prof. Hai (Helen) Li (PI)
Sponsors: Defense Advanced Research Projects Agency
Team Members: Miao HuChenchen Liu, Bonan Yan, and Chaofei Yang
Collaborators: Dr. Qing Wu, U.S. Air Force Research Lab
Dr. Jianhua Yang, HP Labs
 Starting Date:  06/01/2013

Related Publications:

[In Press]

[2014]

[TNNLS]

M. Hu, H. Li, Y. Chen, Q. Wu, G. Rose, and R. Linderman, “Memristor Crossbar Based Neuromorphic Computing System: A Case Study,” IEEE Transactions on Neural Networks and Learning Systems (TNNLS), vol. 25, no 10, pp. 1864-1878, Oct. 2014. DOI: 10.1109/TNNLS.2013.2296777.download-icon

[ISVLSI]
H. Li, M. Hu, C. Li, and S. Duan, “Memristor Modeling – Static, Statistical, and Stochastic Methodologies,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul. 2014, to appear. (Invited)

[ISVLSI]
C. Liu, and H. Li, “A Weighted Sensing Scheme for ReRAM-based Cross-point Memory Array,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Jul. 2014, to appear. (Best Paper Award)

[IJCNN]
X. Hu, G. Feng, H. Li, Y. Chen and S. Duan, “An Adjustable Memristor Model and Its Application in Small-world Neural Networks,” International Joint Conference on Neural Networks (IJCNN), Jul. 2014, pp. 7-14. DOI: 10.1109/IJCNN.2014.6889605.download-icon

[IJCNN]
L. Chen, C. Li, T. Huang, X. He, H. Li and Y. Chen, “STDP Learning Rule Based on Memristor with STDP Property,” International Joint Conference on Neural Networks (IJCNN), Jul. 2014, pp. 1-6. DOI: 10.1109/IJCNN.2014.6889506.download-icon

[ISCAS]
Q. Wu, B. Liu, Y. Chen, H. Li, Q. Chen, and Q. Qiu, “Bio-Inspired Computing with Resistive Memories – Models, Architectures and Applications,” IEEE International Symposium on Circuits and Systems (ISCAS), Jun. 2014, pp. 834-837. DOI: 10.1109/ISCAS.2014.6865265. (Invited)download-icon

[ASPDAC]
M. Hu, Y. Wang, Q. Qiu, Y. Wang, Y. Chen, and H. Li, “The Stochastic Modeling of TiO2 Memristor and Its Usage in Neuromorphic System Design,” Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2014, pp. 831-836. DOI: 10.1109/ASPDAC.2014.6742993.download-icon