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Year
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2015
P. Wang, E. Eken, W. Zhang, R. Joshi, R. Kanj, Y. Chen, “A Thermal and Process Variation Aware MTJ Switching Model and Its Applications in Soft Error Analysis” Springer DOI: 978-14-939-2162-1
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2015
W. Wen, Y. Zhang, Y. Chen, “Statistical Reliability/Energy Characterization in STT-RAM Cell Designs” Springer DOI: 978-3-319-15179-3
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2015
Y.-C. Chen, W. Zhang, Y. Chen, H. Li, “In-place Logic Obfuscation for Emerging Nonvolatile FPGAs” Springer DOI: to appear
2015
K. Nixon, L. Chen, Y. Chen, Z.-H. Mao, “User Classification and Authentication for Mobile Device Based on Continuous Gesture” Springer DOI: to appear
2015
H. Li , M. Hu, , “Modeling of Memristor at nanoscale ? Static, Statistical, and Stochastic Methodologies” Springer DOI: to appear

[APA]
2015
L. Zhang, N. Ge, J. J. Yang, Z. Li, R.S. Williams, Y. Chen, “Low Voltage Two-state-variable Memristor Model of Vacancy-drift Resistive Switches” Springer, vol. 119, no. 1?pp.1-9 DOI: 10.1007/s00339-015-9033-3
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[CCCF]
2015
Y. Chen, H. Li, C. Wu, B. Liu, C. Liu, M. Mao, W. Wen, “Neuromorphic Computing based on Emerging Devices” DOI: to appear

[JCSU]
2015
D. Wang, H.-P. Liu, Y. Chen, “Multi-bit Soft Error Tolerable L1 Data Cache Based on Characteristic of The Data Value” DOI: to appear

[MP]
2015
Y. Chen, W. Zhao, Z. Sun, Y. Zhang, “Emerging Nonvolatile Memory” DOI: to appear

[NCA]
2015
S. Duan, Z. Dong, X. Hu, X. Hu, L. Wang, H. Li, “Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition”, Volume 2015 DOI: 10.1007/s00521-015-1899-7
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[NN]
2015
S. Wen, Z. Zeng, T. Huang, Y. Chen, P. Li, “Circuit Design and Exponential Stabilization of Memristive Neural Networks”, pp. 48-56 DOI: 10.1016/j.neunet.2014.10.011

[NPL]
2015
B. Liu, Y. Chen, B. Wysocki, T. Huang, “Reconfigurable Neuromorphic Computing System with Memristor-Based Synapse Design” Springer, vol. 41, no. 2, pp. 159-167 DOI: 10.1007/ s11063-013-9315-8
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[TC]
2015
Q.Li, J. Li, L. Shi, C. J. Xue, Y. Chen, Y. He, “Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache” IEEE DOI: 10.1109/TC.2014.2360527

[TC]
2015
Z. Sun, X. Bi, W. Wu, S. Yoo, H. Li, “Array Organization and Data Management Exploration in Racetrack Memory” IEEE DOI: 10.1109/TC.2014.2360545
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[TCAD]
2015
B. Li, P. Gu, Y. Shan, Y. Wang, Y. Chen, H. Yang, “RRAM-based Analog Approximate Computing” IEEE DOI: to appear

[TED]
2015
Y. Zhang, B.N. Yan, W. Kang, Y.Q. Cheng, J-O Klein, Y.G. Zhang, Y. Chen , W.S. Zhao, “Compact Model of Subvolume MTJ and its Design Application at Nanoscale Technology Nodes” IEEE DOI: 10.1109/TED.2015.2414721

[TVLSI]
2015
Y. Zhang, Y. Li, Z. Sun, H. Li, A. K. Jones, Y. Chen, “Read Performance: The Newest Barrier in Scaled STT-RAM” IEEE, pp. 1170-1174 DOI: 10.1109/TVLSI.2014.2326797
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[ASPDAC]
2015
C. Zhang, G. Sun, W. Zhang, F. Mi, H. Li, W. Zhao, “Quantitative Modeling of Racetrack Memory, A Tradeoff among Area, Performance, and Power”, pages 100-105 DOI: 10.1109/ASPDAC.2015.7058988

[ASPDAC]
2015
X. Liu, M. Mao, X. Bi, H. Li, Y. Chen, “An efficient STT-RAM-based register file in GPU architectures”, pp. 490 – 495 DOI: 10.1109/ASPDAC.2015.7059054
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[ASP-DAC]
2015
M. Xie, C. Pan, J. Hu, Y. Chen, C. Yang, “Checkpoint-aware Instruction Scheduling for Nonvolatile Processor with Multiple Functional Units”, pp. 316-321 DOI: 10.1109/ASPDAC.2015.7059024

[DAC]
2015
S. Gu, Q. Zhuge, J. Hu, Y. Chen, E. Sha, “Area and Performance Co-optimization for Domain Wall Memory in Application-specific Embedded Systems” DOI: to appear

[DAC]
2015
W. Wen, C.-R. Wu, X. Hu, B. Liu, T.-Y. Ho, X. Li, “An EDA Framework for Large Scale Hybrid Neuromorphic Computing Systems” DOI: to appear

[DAC]
2015
C. Liu, B. Yan, C. Yang, L. Song, Z. Li, B. Liu, “A Spiking Neuromorphic Design with Resistive Crossbar” DOI: to appear

[DAC]
2015
B. Liu, X. Li, Q. Wu, T. Huang, H. Li, Y. Chen, “Vortex: Variation-aware Training for Memristor X-bar” DOI: to appear

[DAC]
2015
J. Guo, W. Wen, J. Hu, D. Wang, H. Li, Y. Chen, “FlexLevel: a Novel NAND Flash Storage System Design for LDPC Latency Reduction” DOI: to appear

[DAC]
2015
M. Mao, J. Hu, Y. Chen, H. Li, “VWS: A Versatile Warp Scheduler for Exploring Diverse Cache Localities of GPGPU Applications” DOI: to appear

[DAC]
2015
X. Liu, M. Mao, B. Liu, B. Li, H. Jiang, Y. Wang, M. Barnell, Q. Wu, J. Yang, H. Li, Y. Chen, “Reno: A Highly-efficient Reconfigurable Neuromorphic Computing Accelerator Design” DOI: to appear

[DAC]
2015
Xiang Chen, Jason Chun Xue, Yiran Chen, “DaTuM: Dynamic Tone Mapping Technique for OLED Display Power Saving based on Video Classification” DOI: to appear

[DAC]
2015
B. Liu, Q. Wu, H. Li, Q. Qiu, Y. Chen, “Cloning Your Mind: Security Concerns in Cognitive System Designs and Their Solutions” DOI: to appear

[DAC]
2015
X. Zhang, G. Sun, Y. Zhang, W. Wen, Y. Chen, J. Di, “err-PUF: Exploiting Cell Error Distribution for Secure NVM Authentication” DOI: to appear

[DATE]
2015
Y. Zhang, B. Yan, W. Wu, H. Li, Y. Chen, “Giant spin hall effect (GSHE) logic design for low power application” DOI: 10.7873/DATE.2015.1118
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[DATE]
2015
Y. Zhang, W. Wu, Y. Chen, “Spintronic Logic Gates Based on Giant Spin Hall Effect (GSHE) MTJ Element” ACM, pp. 1000-1005 DOI: 978-3-9815-3704-8
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[DATE]
2015
T. Tang, L. Xia, B. Li, R. Luo, Y. Wang, Y. Chen, H. Yang, “Spiking Neural Network with RRAM: Can We Use It for Real-World Application?” ACM, Pages 860-865
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[FCCM]
2015
S. Li, C. Wu, H. Li, B. Li, Y. Wang, Q. Qiu, “FPGA Acceleration of Recurrent Neural Network based Language Model” IEEE, pp. 1810 – 1823 DOI: 10.1109/TIE.2007.898279
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[GLSVLSI]
2015
Y. Wang, W. Wen, M. Hu, H. Li, “A Novel True Random Number Generator Design Leveraging Emerging Memristor Technology” ACM, Pages 271-276 DOI: 10.1145/2742060.2742088
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[GLSVLSI]
2015
B. Yan, Y. Zhang, Z. Li, J. Yang, W. Zhao, P. Chia, “A High?Speed Robust NVM?TCAM Design Using Body Bias Feedback” ACM, Pages 69-74 DOI: 10.1145/2742060.2742077
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[GLSVLSI]
2015
Y. Wang, T. Tang, L. Xia, B. Li, P. Gu, H. Li, Y. Xie, H. Yang, “Energy Efficient RRAM Spiking Neural Network for Real Time Classification” DOI: to appear
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[GLSVLSI]
2015
W. Wen, B. Li, Y. Chen, “EDA Challenges for Memristor-Crossbar based Neuromorphic Computing” ACM, Pages 185-188 DOI: 10.1145/2742060.2743754
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[InterMag]
2015
E. Eken, Y. Zhang, B. Yan, W. Wen, H. Li, Y. Chen, “Spin-Hall Assisted STT-RAM Design and Discussion” DOI: to appear

[ISCAS]
2015
Z. Li, B. Yan, L. Yang, W. Zhao, H. Li, Y. Chen, “A New Self-Reference Sensing Scheme for TLC MRAM” IEEE DOI: to appear

[ISCAS]
2015
H. Li, B. Liu, X. Liu, M. Mao, Y. Chen, Q. Wu, Q. Qiu, “The Applications of Memristor Devices in Next-generation Cortical Processor Designs” DOI: to appear

[NeuComp]
2015
H. Li, B. Liu, X. Liu, M. Mao, Y. Chen, Q. Wu, Q. Qiu, “The Applications of Memristor Devices in Next-generation Cortical Processor Designs” DOI: to appear
2014
Y. Zhang, W. Wen, H. Li, Y. Chen, “The Prospect of STT-RAM Scaling” CRC DOI: 978-14-665-8844-8
2014
Y. Chen, H. Li , Z. Sun, “Spintronic Memristor as Interface between DNA and Solid State Devices,” Springer DOI: 978-1-4614-9067-8
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2014
H. Li, Z. Sun, X. Bi, W.-F. Wong, X. Zhu, W. Wu, “STT-RAM Cache Hierarchy Design and Exploration with Emerging Magnetic Devices” Springer DOI: 978-1-4419-9550-6
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[CSU]
2014
K. Bu, Y. Chen, H. Xu, W. Yi, Q. Xie, “NAND Flash Service Lifetime Estimate with Recovery Effect and Retention Time Relaxation”, pp. 3205-3213 DOI: 10.1007/s11771-014-2292-x
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[NCA]
2014
L. Chen, C. Li, T. Huang, Y. Chen, X. Wang, “Memristor Crossbar-based Unsupervised Image Learning”, vol. 25, no. 2, pp. 393-400 DOI: 10.1007/ s00521-013-1501-0
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[PLA]
2014
L. Chen, C. Li, T. Huang, H. G. Ahmad, Y. Chen, “A Phenomenological Memristor Model for Short-term/long-term Memory”, vol. 378, no. 40, pp. 2924?2930 DOI: 10.1016/j.physleta.2014.08.018
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[SWJ]
2014
Z. Dong, S. Duan, X. Hu, L. Wang, H. Li, “A Novel Memristive Multilayer Feedforward Small-World Neural Network with its Applications in PID Control”, Volume 2014?Article ID 394828 DOI: 10.1155/2014/394828
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[TCAD]
2014
W. Wen, Y. Zhang, Y. Wang, Y. Chen, Y. Xie, “PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method” IEEE, vol. 33, no. 11, pp. 1644-1656 DOI: 10.1109/TCAD.2014.2351581
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[TMAG]
2014
E. Eken, Y. Zhang, W. Wen, R. Joshi, H. Li, Y. Chen, “A Novel Self-Reference Technique for STT-RAM Read and Write Reliability Enhancement” IEEE, vol. 50, no. 11, article no. 3401404 DOI: 10.1109/TMAG.2014.2323196
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[TNNLS]
2014
M. Hu, H. Li, Y. Chen, Q. Wu, G. Rose, R. Linderman, “Memristor Crossbar Based Neuromorphic Computing System: A Case Study” IEEE, vol. 25, no 10, pp. 1864-1878 DOI: 10.1109/TNNLS.2013.2296777
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[TVLSI]
2014
Z. Sun, X. Bi, H. Li, W. F. Wong, X. Zhu, “STT-RAM Cache Hierarchy With Multiretention MTJ Designs” IEEE, vol. 22, no 6. pp. 1281-1293 DOI: 10.1109/TVLSI.2013.2267754
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[TVLSI]
2014
Z. Sun, X. Bi, H. Li, W.-F. Wong, X. Zhu, “STT-RAM Cache Hierarchy with Multi-retention MTJ Designs” IEEE, volume 22, issue 6, pages 1281-1293 DOI: 10.1109/TVLSI.2013.2267754
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[ASP-DAC]
2014
B. Li, Y. Wang, H. Yang, J. Wong, Y. Chen, “Training Itself: Mixed-signal Training Acceleration for Memristor-based Neural Network” IEEE, pp.361-366 DOI: 10.1109/ASPDAC.2014.6742916
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[ASP-DAC]
2014
J. Guo, Z. Chen, D. Wang, Z. Shao, Y. Chen, “DPA: A data pattern aware error prevention technique for NAND flash lifetime extension” IEEE, pp.592-597 DOI: 10.1109/ASPDAC.2014.6742955
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[ASP-DAC]
2014
M. Hu, Y. Wang, Q. Qiu, Y. Wang, Y. Chen, H. Li, “The Stochastic Modeling of TiO2 Memristor and Its Usage in Neuromorphic System Design” IEEE, pp.831-836 DOI: 10.1109/ASPDAC.2014.6742993
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[ASP-DAC]
2014
X. Liu, Y. Li, Y. Zhang, A.K. Jones, Y. Chen, “STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures” IEEE, pp. 355 – 360 DOI: 10.1109/ASPDAC.2014.6742915
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[ASP-DAC]
2014
M. Mao, G. Sun, Y. Li, A. Jones, Y. Chen, “Prefetching techniques for STT-RAM based last-level cache in CMP systems” IEEE, 67 – 72 DOI: 10.1109/ASPDAC.2014.6742868
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[ASP-DAC]
2014
J. Wang, Y. Tim, W.-F. Wong, Z.-L. Ong, Z. Sun, H. Li, “A Coherent Hybrid SRAM and STT-RAM L1 Cache Architecture for Shared Memory Multicores” IEEE, pages 610-615 DOI: 10.1109/ASPDAC.2014. 6742958
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[CODES+ISSS]
2014
C. Pan, J. Hu, Y. Chen, “3M-PCM: Exploiting Multiple Write Modes MLC Phase Change Main Memory in Embedded Systems”, article no. 33 DOI: 10.1145/2656075.2656076

[DAC]
2014
B. Liu, X. Li, T. Huang, Q. Wu, M. Barnell, H. Li, “Model Reduction and IR-drop Compensations Techniques for Reliable Neuromorphic Computing Systems” IEEE
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[DAC]
2014
W. Wen, M. Mao, Y. Zhang, Y. Chen, “State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System” IEEE, pp. 1-6 DOI: 10. 1145/2593069.2593220

[DAC]
2014
M. Sun, L. E. Burke, Z.-H. Mao, Y. Chen, H.-C. Chen, Y. Bai, Y. Li, C. Liu, W. Jia, “eButton: A Wearable Computer for Health Monitoring and Personal Assistance” IEEE, pp. 1-6 DOI: 10.1145/2593069.2596678

[DAC]
2014
X. Chen, Y. Chen, M. Dong, C. Zhang, “Demystifying Energy Usage in Smartphones” IEEE, pp. 1-5 DOI: 10.1145/2593069.2596676

[DAC]
2014
E. Eken, Y. Zhang, W. Wen, R. Joshi, H. Li, Y. Chen, “A new field-assisted access scheme of STT-RAM with self-reference capability” IEEE, pp. 1-6 DOI: DOI: 10.1145/2593069.2593075
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[DAC]
2014
M. Mao, W. Wen, Y. Zhang, Y. Chen, H. Li, “Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory” IEEE/ACM, 1–6 DOI: 10.1145/2593069.2593137
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[DAC]
2014
B. Liu, M. Barnell, Q. Wu, T. Huang, X. Li, Y. Chen, “Reduction and IR-drop Compensations Techniques for Reliable Neuromorphic Computing Systems” IEEE/ACM, 63 – 70 DOI: 10.1109/ICCAD.2014.7001330
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[DAC]
2014
Xiang Chen, Mian Dong , Charlie Zhang, Yiran Chen, “Demystifying Energy Usage in Smartphones” IEEE/ACM, 1~5 DOI: 10.1145/2593069.2596676
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[DATE]
2014
B. Li, Y. Wang, Y. Chen, H. Li, H. Yang, “ICE: Inline Calibration for Memristor Crossbar-based Computing Engine”, pp. 1-4 DOI: 10.7873/ DATE.2014.197

[DATE]
2014
Y. Wang, B. Li, R. Luo, Y. Chen, “Energy Efficient Neural Networks for Big Data Analytics” IEEE, pp.1-2 DOI: 10.7873/DATE.2014.358
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[DATE]
2014
E. Park, S. Yoo, S. Lee, H. Li, “Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation” IEEE, pages 1-4 DOI: 10.7873/DATE2014.172
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[DSTA/ICNC]
2014
D. Wang, J. Guo, K. Bu, Y. Chen, “Reduction of Data Prevention Cost and Improvement of Reliability in MLC NAND Flash Storage System”, pp. 259-263 DOI: 10.1109/ICCNC.2014.6785342

[HotPower]
2014
K. Nixon, X. Chen, H. Zhou, Y. Liu, Y. Chen, “Mobile GPU power consumption reduction via dynamic resolution and frame rate scaling” USENIX, 5 – 5 DOI: N/A
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[HPEC]
2014
X. Liu, M. Mao, H. Li, Y. Chen, H. Jiang, J. Yang, “A heterogeneous computing system with memristor-based neuromorphic accelerators” IEEE, PP. 1 – 6 DOI: 10.1109/HPEC.2014.7040986
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[ICCD]
2014
J. Wang, W.-F. Wong, H. Li, “Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration” IEEE, 133 – 138 DOI: 10.1109/ICCD.2014.6974672
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[IJCNN]
2014
L. Chen, C. Li, T. Huang, X. He, H. Li, Y. Chen, “STDP Learning Rule Based on Memristor with STDP Property” IEEE, pp.1-6 DOI: 10.1109/IJCNN.2014.6889506
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[IJCNN]
2014
X. Hu, G. Feng, H. Li, Y. Chen, S. Duan, “An Adjustable Memristor Model and Its Application in Small-world Neural Networks” IEEE, pp.7-14 DOI: 10.1109/IJCNN.2014.6889605
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[ISCAS]
2014
Q. Wu, B. Liu, Y. Chen, H. Li, Q. Chen, Q. Qiu, W. Zhang, “Bio-inspired Computing with Resistive Memories?Models, Architectures and Applications” IEEE, pp. 834-837 DOI: 10.1109/ISCAS.2014.6865265
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[ISCAS]
2014
Q. Wu, B. Liu, Y. Chen, H. Li, Q. Chen, Q. Qiu, “Bio-Inspired Computing with Resistive Memories ? Models, Architectures and Applications” IEEE, pp. 834-837 DOI: 10.1109/ISCAS.2014.6865265

[ISCE]
2014
W. Wen, Y. Zhang, M. Mao, Y. Chen, “STT-RAM Reliability Enhancement through ECC and Access Scheme Optimization”, pp. 22-25 DOI: 10.1109/ISCE.2014.6884324

[ISIC]
2014
H. Li, X.Liu, M. Mao, Y. Chen, Q. Wu, M. Barnell, “Neuromorphic Hardware Acceleration Enabled by Emerging Technologies”, pages 124-127 DOI: 10.1109/ISICIR.2014.7029530

[ISLPED]
2014
C. Zhang, G. Sun, P. Li, T. Wang, D. Niu, Y. Chen, “SBAC: A Statistics based Cache Bypassing Method for Asymmetric-access Caches” ACM, pp.345-350 DOI: 10.1145/2627369.2627611
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[ISLPED]
2014
Z. Sun, X. Bi, A. K. Jones, H. Li, “Design Exploration of Racetrack Lower-level Caches” ACM DOI: 10.1145/2627369.2627651
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[ISNN]
2014
X. Li, S. Duan, L. Wang, T. Huang, Y. Chen, “Memristive Radial Basis Function Neural Network for Parameters Adjustment of PID Controller” DOI: 10.1007/978-3-319-12436-0_17

[ISVLSI]
2014
C. Liu, H. Li, , “A Weighted Sensing Scheme for ReRAM-Based Cross-Point Memory Array” IEEE, pp. 65-70 DOI: 10.1109/ISVLSI.2014.32
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[NVMSA]
2014
I. Bayram, Y. Chen, , “NV-TCAM: Alternative interests and practices in NVM designs” IEEE, pp. 1-6 DOI: 10.1109/NVMSA.2014.6927206
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[CSAW]
2014
Y.-C. Cheng, C. Yang, H. Li, “Evaluation of In-place Logic Obfuscation Proposed for ReRAM FPGA” the Final Phase in Embedded Security Challenge (ESC) during NYU?s CyberSecurity Awareness Week (CSAW)

[DAAMSC]
2014
B. Liu, T. Huang, Q. Wu, M. Barnell, X. Li, Y. Chen, “Reduction and IR-drop Compensations Techniques for Reliable Neuromorphic Computing”

[FPGA]
2014
F. Mao, Y.-C. Chen, W. Zhang, H. Li, “BMP: A Fast B*-Tree based Modular Placer for FPGAs” ACM, N/A DOI: 10.1145/2554688.2554755
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[HotPower]
2014
Xiang Chen, Kent W. Nixon, Hucheng Zhou, Yunxin Liu, Yiran Chen, “FingerShadow: An OLED Power Optimization Based on Smartphone Touch Interactions” USNIX / OSDI, No. 5 DOI: N/A
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[HotPower]
2014
Kent W. Nixon, Xiang Chen, Hucheng Zhou, Yunxin Liu, Yiran Chen, “Mobile GPU Power Consumption Reduction via Dynamic Resolution and Frame Rate Scaling” USNIX / OSDI, No. 6 DOI: N/A
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[InterMag]
2014
E. Eken, Y. Zhang, W. Wen, R. Joshi, H. Li, Y. Chen, “A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability”

[ISFGA]
2014
H. Liang, Y.-C. Chen, W. Zhang, H. Li, “BMP: A Fast B*-Tree based Modular Placer for FPGAs” the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

[ISIC]
2014
T. Tang, B. Li, Y. Wang, R. Luo, H. Li, “Energy Efficient Spiking Neural Network Design with RRAM Devices” IEEE, pages 268-271 DOI: 10.1109/ISICIR.2014.7029565
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[ISVLSI]
2014
H. Li, M. Hu, C. Li, S. Duan, “Memristor Modeling ? Static, Statistical, and Stochastic Methodologies” IEEE, pp.406 – 411 DOI: 10.1109/ISVLSI.2014.108
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[SiPS]
2014
Q. Qiu, Z. Li, K. Ahmed, H. Li, M. Hu, “Neuromorphic Acceleration for Context Aware Text Image Recognition” IEEE, pages 1-6 DOI: 10.1109/SiPS.2014.6986098
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[SoCC]
2014
H. Li, M. Hu, X. Liu, M. Mao, C. Li, S. Duan, “Emerging Memristor Technology Enabled Next Generation Cortical Processor” IEEE, pp.377 – 382 DOI: 10.1109/SOCC.2014.6948958
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[ACM SIGBED]
2013
L. Niu, L. Medina, Y. Chen, “Reliability-aware Energy Minimization for Real-time Embedded Systems with Window-constraints” ACM, Volume 10 Issue 2 DOI: 10.1145/2518148.2518164
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[APL]
2013
L. Zhang, Z. Chen, J. J. Yang, B. Wysocki, N. McDonald, Y. Chen, “A Compact Modeling of TiO2-TiO2-x Memristor” AIP, vol. 102, no. 15, 153503 (2013) DOI: 10.1063/ 1.4802206
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[ENEHPEA/TACO]
2013
Y. Li, Y. Zhang, H. Li, Y. Chen, A. Jones, “C1C: A Configurable, Compiler-guided STT-RAM L1 Cache” ACM, vol. 10, no. 4, article 52 DOI: 10.1145/2541228.2555308
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[JETC]
2013
Y. Chen, W. Wong, H. Li, C.-K. Koh, Y. Zhang, W. Wen, “On-chip Caches built on Multi-Level Spin-Transfer Torque RAM Cells and Its Optimizations” ACM, vol. 9, no 2, article 16 DOI: 10.1145/2463585.2463592
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[Journal of the Franklin Institute]
2013
S. Wen, Z. Zeng, T. Huang, Y. Chen, “Passivity Analysis of Memristor-based Recurrent Neural Networks with Time-varying Delays” Elsevier, vo. 350, no. 8, pp. 2354-2370. DOI: 10.1016/j.jfranklin.2013.05.026
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[NN]
2013
S. Wen, G. Bao, Z. Zeng, Y. Chen, T. Huang, “Global Exponential Synchronization of Memristor-based Recurrent Neural Networks with Time-varying Delays” Elsevier, vol. 48, pp. 195-203 DOI: 10.1016/j.neunet.2013.10.001
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[PLA]
2013
L. Chen, C. Li, T. Huang, Y. Chen, S. Wen, J. Qi, “A Synapse Memristor Model with Forgetting Effect” Elsevier, vol. 377, no. 45-48,pp. 3260-3265 DOI: 10.1016/j.physleta.2013.10. 024
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[PLA]
2013
S. Wen, Z. Zeng, T. Huang, Y. Chen, “Fuzzy Modeling and Synchronization of Different Memristor-based Chaotic Circuits” Elsevier, vol. 377, no. 34?36, pp. 2016?2021 DOI: 10.1016/j. physleta.2013.05.046
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[TODAES]
2013
B. Zhao, J. Yang, Y. Zhang, Y. Chen , H. Li, “Common-Source-Line Array: An Area Efficient Memory Architecture for Bipolar Nonvolatile Devices” ACM, vol. 18, no. 4, article 57 DOI: 10.1145/2500459
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[TODAES]
2013
J. Li, L. Shi, Q. Li, C. Xue, Y. Chen, Y. Xu, W. Wang, “Low-Energy Volatile STT-RAM Cache Design Using Cache Coherence Enabled Adaptive Refresh” ACM, vol. 19, no. 1, article 5 DOI: 10.1145/2534393
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[ASPDAC]
2013
Kent W. Nixon, Xiang Chen, Zhihong Mao, Kang Li, Yiran Chen, “” IEEE, 384~389 DOI: 10.1109/ASPDAC.2013.6509626
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[ASP-DAC]
2013
W. Wen, Y. Zhang, L. Zhang, Y. Chen, “Loadsa: A Yield-Driven Top-Down Design Method for STT-RAM Array” IEEE, pp.291 – 296 DOI: 10.1109/ASPDAC.2013.6509611
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[ASP-DAC]
2013
K. Nixon, X. Chen, Z.H. Mao, Y. Chen, K. Li, “Mobile User Classification and Authorization Based on Gesture Usage Recognition” IEEE, pp.384-389 DOI: 10.1109/ASPDAC.2013.6509626
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[CISDA]
2013
M. Hu, H. Li, Y. Chen, Q. Wu, G. S. Rose, “BSB Training Scheme Implementation on Memristor-Based Circuit” IEEE, pp.80 – 87 DOI: 10.1109/CISDA.2013.6595431
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[CODES+ISSS]
2013
B. Liu, M. Hu, H. Li , Y. Chen, C. Xue, “Bio-inspired Ultra Lower-power Neuromorphic Computing Engine for Embedded Systems” IEEE/ACM/IFIP, p.1 DOI: 10.1109/CODES-ISSS.2013.6659010
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[DAC]
2013
B. Liu, M. Hu, H. Li , Z-H. Mao, Y. Chen, T. Huang, “Digital-Assisted Noise Eliminating Training for Memristor Crossbar-based Analog Neuromorphic Computing Engine” IEEE, pp. 1-6 DOI: 10.1145/2463209.2488741
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[DAC]
2013
Xiang Chen, Zhan Ma, Felix C. A. Fernandes, Jason Chun Xue, Yiran Chen, Q. Wu, H. Jiang, Y. Chen, H. Li, “Dynamic Tone Mapping on OLED Display Based on Video Classification” IEEE/ACM, WiP DOI: N/A
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[DAC]
2013
Xiang Chen, Hai Helen Li, , “P-Spectrum: A Personalized Smartphone Power Management Technique based on Real-time Battery and User Behavior Monitoring” IEEE/ACM, WiP DOI: N/A
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[DAC]
2013
Kent W. Nixon, Xiang Chen, Zhihong Mao, Kang Li, Yiran Chen, “The Invisible Shield: User Classification and Authentication for Mobile Device Based on Gesture Recognition” IEEE/ACM, WiP DOI: N/A
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[DAC]
2013
Z. Sun, W. Wu, H. Li, “Cross-Layer Racetrack Memory Design For Ultra High Density And Low Power Consumption” IEEE, pp. 1 – 6 DOI: 10.1145/2463209.2488799
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[DATE]
2013
X. Bi, M.A. Weldon, H. Li, “STT-RAM Cell Design to Support Dual-Port Access” IEEE, pp. 853-858 DOI: 10.7873/DATE.2013.180
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[DATE]
2013
J. Guo, J. Yang, Y. Zhang, Y. Chen, “Low Cost Power Failure Protection for MLC NAND Flash Storage Systems with PRAM/DRAM Hybrid Buffer” IEEE, pp.859 – 864 DOI: 10.7873/DATE.2013.181
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[DATE]
2013
J. Li, L. Shi, Q. Li, C.J. Xue, Y. Chen, Y. Xu, “Cache Coherence Enabled Adaptive Refresh for Volatile STT-RAM” IEEE, pp.1247 – 1250 DOI: 10.7873/DATE.2013.258
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[DATE]
2013
J. Guo, W. Wen, Y. Zhang, S. Li, H. Li, Y. Chen, “DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems” IEEE, pp.380-385 DOI: 10.7873/DATE.2013.087
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[DATE]
2013
X. Bi, A. M. Weldon, H. Li, “STT-RAM Designs Supporting Dual-port Accesses” IEEE, pp. 853 – 858 DOI: 10.7873/DATE.2013.180
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[FPL]
2013
Y.-C. Chen, W. Zhang, H. Li, “A Hardware Security Scheme for RRAM-based FPGA” IEEE, pp. 1-4 DOI: 10.1109/FPL.2013.6645556
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[GLSVLSI]
2013
M. Mao, H. Li, A. Jones, Y. Chen, “Coordinating Prefetching and STT-RAM-based Last-level Cache Management for Multicore Systems” ACM, pp.55-60 DOI: 10.1145/2483028.2483060
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[ICCAD]
2013
A. Jones, Y. Chen, W.O. Collinge, H. Wu, L. Schaefer, A.E. Landis, M.M. Bilec, “Considering Fabrication in Sustainable Computing” IEEE, pp.206 – 210 DOI: 10.1109/ICCAD.2013.6691120
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[ICCAD]
2013
X. Bi, M. Mao, D. Wang, H. Li, “Unleashing the potential of MLC STT-RAM caches” IEEE, pp. 429-436 DOI: 10.1109/ICCAD.2013.6691153
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[ICCAD]
2013
Y. Zhang, I. Bayram, Y. Wang, H. Li, Y. Chen, Q. Wu, M Barnell, “ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications” IEEE, pp.9 – 16 DOI: 10.1109/ICCAD.2013.6691091
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[ICCAD]
2013
W. Wen, M. Mao, S. Kang, X. Zhu, D. Wang, Y. Chen, “CD-ECC: Content-Dependent Error Correction Codes for Combating Asymmetric Nonvolatile Memory Operation Errors” IEEE, pp.1-8 DOI: 10.1109/ICCAD.2013.6691090
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[ICHSCSS]
2013
Mengying Zhao, Xiang Chen, Yiran Chen, Jason Chun Xue, “Online OLED Dynamic Voltage Scaling for Video Streaming Applications on Mobile Devices” IEEE CODES+ISSS, pp.1 – 10 DOI: 10.1109/CODES-ISSS.2013.6658996
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[IJCNN]
2013
F. Ji, H. Li, B. Wysocki, C. Thiem, N. McDonald, “Memristor-based Synapse Design and a Case Study in Reconfigurable Systems” IEEE, pp. 1 – 6 DOI: 10.1109/IJCNN.2013.6706776
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[ISCAS]
2013
Y. Zhang, L. Zhang, Y. Chen, “MLC STT-RAM Design Considering Probabilistic and Asymmetric MTJ Switching” IEEE, pp. 113-116 DOI: 10.1109/ISCAS.2013.6571795
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[ISCAS]
2013
Y. Zhang, L. Zhang, Y. Chen, “MLC STT-RAM design considering probabilistic and asymmetric MTJ switching” IEEE, pp.113-116 DOI: 10.1109/ISCAS.2013.6571795
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[ISLPED]
2013
B. Li, M. Hu, Y. Wang, Y. Chen, H. Yang, “Memristor-based Approximated Computation” IEEE, pp.242-247 DOI: 10.1109/ISLPED.2013.6629302
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[ISLPED]
2013
J. Wang, Z. Sun, H. Li, W.-F. Wong, “Practical Low-Power Memristor-based Analog Neural Branch Predictor” ACM, pp. 175-180 DOI: 10.1109/ISLPED.2013.6629290
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[DAAMSC]
2013
Y. Zhang, I. Bayram, Y. Wang, H. Li, Y. Chen, “ADAMS: Asymmetric Differential STT-RAM Cell Structure for Reliable and High-performance Applications” DOI: 10.1109/ICCAD.2013.6691091
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[ISDRS]
2013
J. Guo, G. Sun, J. Xue, H. Li, “The Stochastic Characteristics of Memristor Devices and Case Studies in Neuromorphic Hardware Design” ISDRS
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[MCSA]
2013
Xiang Chen, Yiran Chen, Zhan Ma, Felix C. A. Fernandes, “How is Energy Consumed in Smartphone Display Applications?” ACM, No. 18 DOI: 10.1145/2444776.2444781
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[MeoAW]
2013
M. Mao, G. Sun, Y. Li, A. Jones, Y. Chen, “Prefetching Techniques for STT-RAM based Last-level Cache in CMP Systems”

[NeuComp]
2013
M. Hu, H. Li, G. Rose, Q. Wu, Y. Chen, “Training Scheme Analysis for Memristor-Based Neuromorphic Design”

[SHAW4]
2013
M. Mao, H. Li, A. Jones, J. Xue, Y. Chen, “Dynamic Prefetch Aggressiveness Tuning for STT-RAM-based Last-level Cache”

[DAC]
2013
J. Guo, G. Sun, J. Xue, H. Li, “The Detection of Malicious Data Attack on NAND Flash Storage System based on Power Signature”

[RTSS]
2013
Mengying Zhao, Xiang Chen, Yiran Chen, Jason Chun Xue, Y. Chen, “Online OLED Dynamic Voltage Scaling for Video Streaming Applications on Mobile Devices” ACM, Volum10, Issue2, Pages18 DOI: 10.1145/2518148.2518156
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2012
H. Li , R. E. Pino,, , “Statistical Memristor Model and Its Applications in Neuromorphic Computing” Springer DOI: 978-94-007-4490-5
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[ESL]
2012
Y. Li, Y. Chen, Y. Zhang, A. K. Jones, “Combating Write Penalties Using Software Dispatch for On-chip MRAM Integration” IEEE, vol. 4, no. 4, pp. 82-85 DOI: 10.1109/LES.2012.2216253
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[ICONIP]
2012
B. Liu, Y. Chen, B. Wysocki, T. Huang, “The Circuit Realization of a Neuromorphic Computing System with Memristor-Based Synapse Design” Springer, pp. 357-365 DOI: 10.1007/978-3-642-34475-6_43
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[JETC]
2012
Z. Sun, X. Chen, Y. Zhang, H. Li, Y. Chen, “Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder” ACM, Volum8, Issue2, No.13 DOI: 10.1145/2180878.2180885
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[JSSC]
2012
Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu , T. Zhang, “A 130nm 1.2V/3.3V 16Kb Spin-Transfer Torque Random Access Memory with Nondestructive Self-Reference Sensing Scheme” IEEE, vol. 47, no.2, pp. 560-573 DOI: 10.1109/JSSC.2011.2170778
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[SPIN]
2012
Y. Zhang, W. Wen, Y. Chen, “STT-RAM Cell Design Considering MTJ Asymmetric Switching”, vol. 2, no. 3 DOI: 10.1142/S2010324712400073
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[Spin]
2012
H. Li, Z. Sun, , “Voltage Driven Non-destructive Self-reference Sensing for STT-RAM Yield Enhancement” Spin, volume 2, issue 3, pages 124008 DOI: 10.1142/S2010324712400085
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[TMAG]
2012
X. Bi, H. Li, X. Wang, “STT-RAM Cell Design Considering CMOS and MTJ Temperature Dependence” IEEE, volume 48, issue 11, pp. 3821-3824 DOI: 10.1109/TMAG.2012.2200469
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[TMAG]
2012
Y. Zhang, W. Wen, Y. Chen, “The prospect of STT-RAM scaling from readability perspective” IEEE, vol. 48, no. 11, pp. 3035-3038 DOI: 10.1109/ TMAG.2012.2203589
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[TNANO]
2012
Y.-C. Chen, H. Li, W. Zhang, R. Pino, “The 3D Stacking Bipolar RRAM for High Density” IEEE, volume 11, issue 5, pages 948-956 DOI: 10.1109/TNANO.2012.2208759
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[TVLSI]
2012
Z. Sun, H. Li, Y. Chen, X. Wang, “Voltage Driven Non-Destructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory” IEEE, vol. 20, no. 11, pp. 2020-2030 DOI: 10.1109/TVLSI.2011.2166282
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[ASPDAC]
2012
Y.-C. Chen, W. Zhang, H. Li, “A Look Up Table Design with 3D Bipolar RRAMs” IEEE, pages 73-78 DOI: 10.1109/ASPDAC.2012.6165051
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[ASP-DAC]
2012
Y. Chen, Y. Zhang, P. Wang, “Probabilistic Design in Spintronic Memory and Logic Circuit” IEEE, pp. 323-328 DOI: 10.1109/ ASPDAC.2012.6164967

[ASP-DAC]
2012
X. Chen, J. Zeng, Y. Chen, H. Li, “Fine-grained Dynamic Voltage Scaling on OLED Display” IEEE, pp. 807-812 DOI: 10.1145/2228360.2228540
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[DAC]
2012
W. Wen, Y. Zhang, Y. Chen, Y. Wang, Y. Xie, “PS3-RAM: A Fast, Portable and Scalable Statistical STT-RAM Reliability Analysis Method” IEEE/ACM, pp. 1191-1196 DOI: 10.1145/2228360.2228580

[DAC]
2012
R. Pino, H. Li, Y. Chen, M. Hu, B. Liu, “Statistical Memristor Modeling and Case Study in Neuromorphic Computing” IEEE/ACM, pages 585-590 DOI: 10.1145/2228360.2228466

[DAC]
2012
X. Chen, M. Zhao , J. Zeng, J. Chun Xue, Y. Chen, “Quality-retaining OLED Dynamic Voltage Scaling for Video Streaming Applications on Mobile Devices” IEEE/ACM, pp. 1000-1005 DOI: 10.1145/2228360.2228540
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[DAC]
2012
M. Hu, H. Li, Q. Wu, G. Rose, “Hardware Realization of Neuromorphic BSB Model with Memristor Crossbar Network” IEEE, pages 498-503 DOI: 10.1145/2228360.2228448
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[DATE]
2012
X. Bi, C. Zhang, H. Li, Y. Chen, R. Pino, “Spintronic Memristor Based Temperature Sen- sor Design with CMOS Current Reference”, pp. 1301-1306 DOI: 10.1109/DATE.2012.6176693
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[DATE]
2012
B. Zhao, J. Yang, Y. Zhang, Y. Chen, H. Li, “Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices”, pp. 1451-1454 DOI: 10.1109/DATE.2012.6176594

[DATE]
2012
Y. Zhang, X. Wang, Y. Li, A. Jones, Y. Chen, “Asymmetry of MTJ switching and its implication to STT-RAM designs”, pp. 1313-1318 DOI: 10.1109/DATE.2012.6176695
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[DATE]
2012
X. Bi, H. Li, Y. Chen, R. Pino, “Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference”, pp. 1301-1306 DOI: 10.1109/DATE.2012.6176693

[FPL]
2012
Y.-C. Chen, W. Zhang, H. Li, “Non-volatile 3D stacking RRAM-based FPGA”, pages 367-372 DOI: 10.1109/FPL.2012.6339206
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[FPT]
2012
Y.-C. Chen, W. Wang, W. Zhang, H. Li, “uBRAM-based Run-time Reconfigurable FPGA and Corresponding Reconfiguration Methodology”, pages 80-86 DOI: 10.1109/FPT.2012.6412116
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[ICCAD]
2012
X. Chen, B. Liu, Y. Chen, M. Zhao, J. Xue, X. Guo, “Active Compensation Technique for the Thin-Film Transistor Variations and OLED Aging of Mobile Device Displays” ACM, pp. 516-522 DOI: 10.1145/2429384.2429493

[ICCAD]
2012
X. Bi, Z. Sun, H. Li, W. Wu, “Probabilistic Design Methodology to Improve Run-time Stability and Performance of STT-RAM Caches” IEEE/ACM, pp. 88-94 DOI: 10.1145/2429384.2429401
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[ICCAD]
2012
Y. Chen, X. Chen, M. Zhao, J. Xue, “Mobile Devices User – The Subscriber and also the Publisher of Real-Time OLED Display Power Management Plan” IEEE, pp. 687-690 DOI: 10.1145/2429384.2429534

[ICCAD]
2012
Y. Zhang, L. Zhang, W. Wen, G. Sun, Y. Chen, “Multi-level cell STT-RAM: Is it realistic or just a dream?” ACM, pp.526-532 DOI: 10.1145/2429384.2429498
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[IJCNN]
2012
M. Hu, H. Li, Q. Wu, G. S. Rose, Y. Chen, “Memristor Crossbar Based Hardware Realization of BSB Recall Function” IEEE, pages 1-7 DOI: 10.1109/IJCNN.2012.6252563

[IJCNN]
2012
H. Wang, H. Li, R. E. Pino, “Memristor-based Synapse Design and Training Scheme for Neuromorphic Computing Architecture” IEEE, pages 1-5 DOI: 10.1109/IJCNN.2012.6252577
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[InterMag]
2012
P. Wang, Y. Chen, , “Robustness of MTJ Switching in STT-RAM under Radiation Attack” IEEE, HB-07

[InterMag]
2012
Y. Zhang, J. Wen, Y. Chen, “The Prospect of STT-RAM Scaling from Read ability Perspective” IEEE, BB-03

[ISCAS]
2012
Y.-C. Chen, H. Li, W. Zhang, “A Novel Peripheral Circuit for RRAM-based LUT” IEEE, pages 1811-1814 DOI: 10.1109/ISCAS.2012.6271619
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[ISLPED]
2012
G. Sun, Y. Zhang, Y. Wang, Y.Chen, “Improving Energy Efficiency of Write-Asymmetric Memories by Log Style Write” IEEE, pp. 173-178 DOI: 10.1145/2333660.2333705

[ISLPED]
2012
Y. Li, Y. Chen, A. K. Jones, “A Software Approach for Combating Asymmetries of Non-Volatile Memories” ACM, Pages 191-196 DOI: 10.1145/2333660.2333708

[ISLPED]
2012
Z. Sun, X. Bi, H. Li, “Process Variation Aware Data Management for STT-RAM Cache Design” ACM/IEEE, pages 179-184 DOI: 10.1145/2333660.2333706
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[ISVLSI]
2012
X. Bi, H. Li, J.-J. Kim, “Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design” IEEE, pp. 374-379 DOI: 10.1109/ISVLSI.2012.56
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[ISVLSI]
2012
Z. Shao, Y. Liu, Y. Chen, T. Li, “Utilizing PCM for Energy and Power Optimization in Embedded Systems” IEEE, pp. 398-403 DOI: 10.1109/ISVLSI.2012.81

[SoCC]
2012
H. Li, , , “Memristor in Neuromorphic Computing” IEEE, page 294 DOI: 10.1109/SOCC.2012.6398367
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[DAC]
2012
M. Hu, H. Li, , “Low Power Neuromorphic Circuit Using Memristor Crossbar Array”

[InterMag]
2012
X. Bi, H. Li, X. Wang, “STT-RAM Design Considering Temperature Impact” IEEE

[NVMW]
2012
P. Wang, J. Wu, Y. Chen, “MTJ-based Nonvolatile Latch Design for Standby System”

[NVMW]
2012
Y.-C. Chen, H. Li, W. Zhang, “A RRAM-based Memory System and Applications”

[NVMW]
2012
Z. Sun, X. Bi, H. Li, W.-F. Wong, X. Zhu, W. Wu, “Multi Nonvolatility Level STTRAM Cache Hierarchy”
2011
H. Li, Y. Chen, , “Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing” CRC DOI: 978-14-398-0745-3
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[IET-CDT]
2011
X. Dong, X. Wu, Y. Xie, Y. Chen, H. Li, “Stacking Magnetic Random Access Memory atop Microprocessors: An Architecture-Level Evaluation” IET, vol. 5, no.3, pp. 213-220 DOI: 10.1049/iet-cdt.2009.0091
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[JOLPE]
2011
M. Hu, H. Li, Y. Chen, X. Wang, “Spintronic Memristor: Compact Model and Statistical Analysis” IEEE, vol. 7, no2, pp. 234-244 DOI: 10.1166/jolpe. 2011.1131
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[TMAG]
2011
W. Zhu, H. Li, Y. Chen, X. Wang, “Current Switching in MgO-based Magnetic Tunneling Junctions” IEEE, vol. 47, no 1, part 2, pp.156-160 DOI: 10.1109/ TMAG.2010.2085441
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[TMAG]
2011
Y. Zhang, X. Wang, H. Li, Y. Chen, “STT-RAM cell optimization considering MTJ and CMOS variations” IEEE, vol. 47, no.10, pp. 2962-2965 DOI: 10.1109/TMAG.2011.2158810
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[TMAG]
2011
P. Wang, X. Wang, Y. Zhang, H. Li, S.P. Levitan, Y. Chen, “Nonpersistent Error Optimization in Spin-MOS Logic and Storage Circuitry” IEEE, vol. 47, no10, pp. 3860-3863 DOI: 10.1109/TMAG.2011.2153838
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[TMAG]
2011
Y. Zhang, X. Wang, H. Li, Y. Chen, “STT-RAM Cell Optimization Considering MTJ and CMOS Variations” IEEE, vol. 47, no.10, pp. 2962-2965 DOI: 10.1109/TMAG.2011.2158810
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[TMAG]
2011
H. Li, X. Wang, Z.-L. Ong, W.-F. Wong, Y. Zhang, P. Wang, Y. Chen, “Performance, Power and Reliability Tradeoffs of STT-RAM Cell Subject to Architecture-level Requirement” IEEE, vol. 47, no10, pp. 2356-2359 DOI: 10.1109/TMAG.2011.2159262
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[TVLSI]
2011
W. Xu, H. Sun, X. Wang, Y. Chen,, T. Zhang, “Design of Last-Level On-Chip Cache using Spin-Torque Transfer RAM (STT-RAM)” IEEE, vol. 19, no 3, pp. 483-493 DOI: 10.1109/TVLSI.2009.2035509
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[ASP-DAC]
2011
M. Hu, H. Li, Y. Chen, X. Wang, R. E. Pino, “Geometry Variations Analysis of TiO2?based and Spintronic Memristors” IEEE/ACM, pp. 25-30

[ASP-DAC]
2011
Y. Chen, H. Li, , “Emerging Sensing Techniques for Emerging Memories” ACM, pages 204-210 DOI: 10.1109/ASPDAC.2011.5722185

[CICC]
2011
P. Wang, X. Chen, Y. Chen, H. Li, S. Kang, X. Zhu, W. Wu, “A 1.0 V 45nm Nonvolatile Magnetic Latch Design and Its Robustness Analysis” IEEE, pp 1-4 DOI: 10.1109/CICC.2011.6055392
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[CODES+ISSS]
2011
J. Xue, Y. Zhang, Y. Chen, G. Sun, J. J. Yang, H. Li, “Emerging Non-Volatile Memories: Opportunities and Challenges” ACM, pp.325-334 DOI: 10.1145/2039370.203942
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[Custom Integrated Circuits Conference]
2011
P. Wang, X. Chen, Y. Chen, Hai Helen Li, Seung Kang, Xiaochun Zhu, “A 1.0V 45nm Nonvolatile Magnetic Latch Design and Its Robustness Analysis” IEEE, pp.1~4 DOI: 10.1109/CICC.2011.6055392
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[DAC]
2011
M. Hu, H. Li, Y. Chen, R.E. Pino, “Statistical Model of TiO2 Memristor”

[DATE]
2011
Y.-C. Chen, H. Li, Y. Chen, R. Pino, “3D-ICML: A 3D Bipolar ReRAM Design with Interleaved Complementary Memory” IEEE, pp. 1-4 DOI: 10.1109/DATE.2011.5763289

[ICCAD]
2011
Y. Zhang, X. Wang, Y. Chen, “STT-RAM cell design optimization for persistent and non-persistent error rate reduction: a statistical design view” IEEE, pp.471-477
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[ICCAD]
2011
M. Hu, H. Li, R. E. Pino, “Fast Statistical Model of TiO2 Memristor and Design Implication” ACM, pp 345-352 DOI: 10.1109/ICCAD.2011.6105353
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[ICCAD]
2011
R. Joshi, R. Kanj, P. Wang, H. Li, “Universal Statistical Cure For Predicting Memory Loss” IEEE, pp 236-239 DOI: 10.1109/ICCAD.2011.6105333
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[InterMag]
2011
Y. Zhang, X. Wang, H. Li, Y. Chen, “STT-RAM Cell Optimization Considering Process Variations” IEEE, pp. 2962-2965 DOI: 10.1109/TMAG.2011.2158810

[InterMag]
2011
H. Li, X. Wang, Z.-L. Ong, W.-F. Wong, Y. Zhang, P. Wang , Y. Chen, “Performance, Power and Reliability Tradeoffs of STT-RAM Cell Subjective to Architecture-level Requirement” IEEE, pp. 2356-2359 DOI: 10.1109/TMAG.2011.2159262

[ISLPED]
2011
Y. Chen, W.-F. Wong, H. Li, C.-K. Koh, “Processor Caches built using Multi-Level Spin-Transfer Torque RAM Cells” IEEE, pp. 73-78 DOI: 10.1109/ISLPED.2011.5993610

[MICRO]
2011
Z. Sun, X. Bi, H. Li, W.-F. Wong, Z.-L. Ong, X. Zhu, W. Wu, “Multi Retention Level STT-RAM Cache Designs” ACM, pp. 329-338 DOI: 10.1145/2155620.2155659
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[NANOARCH]
2011
Y.-C. Chen, H. Li, W. Zhang, R. Pino, “3D-HIM: A 3-Dimensional High-Density Interleaved Memory for Bipolar RRAM Design” IEEE, pp 59-64 DOI: 10.1109/NANOARCH.2011.5941484
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[PACT]
2011
P. Zhou, B. Zhao, J. Yang, Y. Zhang, Y. Chen, “MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement” IEEE

[InterMag]
2011
P. Wang, X. Wang, Y. Zhang, H. Li, Y. Chen, “Spin-MOS Logic and Storage Circuitry Optimization for Non-persistent Error Rate Reduction”

[MeoAW]
2011
Y. Li, Y. Chen, Y. Zhang, A.K. Jones, “Software Dispatch: Improving Performance and Power of Hybrid MRAM/SRAM Caches”

[MMM]
2011
X. Bi, H. Li, X. Wang, “Design Considerations for Thermal-assistant STT-RAM through Joule Heating”

[MMM]
2011
Z. Sun, H. Li, X. Wang, “MTJ Design Margin Exploration for Self-Reference Sensing”

[The Non-Volatile Memories Workshop 2011]
2011
Y. Zhang, Y. Chen, X. Wang, H. Li, “STT-RAM Cell Optimization Considering Process Variations”

[The Non-Volatile Memories Workshop 2011]
2011
Y. Chen, X. Wang, W.-F. Wong, H. Li, “Performance, Power and Reliability Tradeoffs of STT-RAM Cell Subjective to Architecture-level Requirement”

[WEST]
2011
Y. Li, Y. Chen, A. Jones, “Magnetic RAM Integration for CMPs using Hardware-Based Software-Optimized Dispatching”

[DAC]
2011
H. Li, X. Wang, Z.-L. Ong, W.-F. Wong, Y. Zhang, P. Wang, Y. Chen, “Statistical Model of TiO2 Memristor”

[EDL]
2010
W. Wang, Y. Chen, Y. Gu, H. Li, “Spintronic Memristor Temperature Sensor” IEEE, pp.20-22 DOI: 10.1109/LED.2009.2035643
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[EDL]
2010
Y. Chen, W. Tian, H. Li, X. Wang, W. Zhu, “PCMO Device with High Switching Stability” IEEE, pp.866-868 DOI: 10.1109/LED.2010.2050457
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[TMAG]
2010
H. Xi, J. Stricklin, H. Li, Y. Chen, X. Wang, Y. Zheng, Z. Gao, M. X. Tang, “Spin Transfer Torque Memory with Thermal Assist Mechanism: A Case Study” IEEE, pp.860-865 DOI: 10.1109/TMAG.2009.2033674
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[TVLSI]
2010
Y. Chen, H. Li, C.-K. Chen, K. Roy, J. Li, G. Sun, “Variable-Latency Adder (VL-Adder): New Arithmetic Circuit Design Practice for Low Power and NBTI Tolerance” IEEE, pp.195-200 DOI: 10.1145/1283780.1283822
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[TVLSI]
2010
W. Xu, T. Zhang, Y. Chen, “Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies” IEEE, vol. 18, no. 12, pp. 1724-1734 DOI: 10.1109/TVLSI.2009.2032192
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[VLSI ]
2010
W. Xu, T. Zhang, Y. Chen, “Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed” IEEE, pp.20-22 DOI: 10.1109/TVLSI.2008.2007735
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[ASQED]
2010
Y. Chen, X. Wang, Z. Sun, H. Li, “The Application of?Spintronic Devices in Magnetic Bio-sensing” IEEE DOI: 10.1109/ASQED.2010.5548244
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[DAC]
2010
D. Niu, Y. Chen, C. Xu, Y. Xie, “Impact of Process Variations on Emerging Memristor” IEEE, pp. 877-882
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[DATE]
2010
X. Wang, Y. Chen, , “Spintronic Memristor Devices and Application” IEEE, pp. 667-672 DOI: 10.1109/DATE.2010.5457118
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[DATE]
2010
Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu, T. Zhang, “A Nondestructive Self-Reference Scheme for Spin-Transfer Torque Random Access Memory (STT-RAM)” IEEE, pp.148-153 DOI: 10.1109/DATE.2010.5457219
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[DATE]
2010
H. Li, M. Hu, , “Compact Model of Memristors and Its Application in Computing Systems” IEEE, pages 673-678 DOI: 10.1109/DATE.2010.5457115
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[HPCA]
2010
G. Sun, Y. Joo, Y. Chen, Y. Xie, Y. Chen, H. Li, “A Hybrid Solid-State Storage Architecture for the Performance, Energy Consumption, and Lifetime Improvement” IEEE, pp. 1-12 DOI: 10.1109/HPCA.2010.5416650
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[ICCAD]
2010
Z. Sun, H. Li, Y. Chen, X. Wang, “Variation Tolerant Sensing Scheme of Spin-Transfer Torque Memory for Yield Improvement” ACM, Pages 432-437
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[ICCCAS]
2010
Y. Chen, H. Li, X. Wang, “Spintronic Devices: from Memory to Memristor” IEEE, pp. 1-4 DOI: 10.1109/ICSICT.2012.6467793
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[ISLPED]
2010
D. Niu, Y. Chen, Y. Xie, “Low-power Dual-element Memristor-Based Memory Design” IEEE
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[ISLPED]
2010
Y. Chen, H. Li, X. Wang, W. Zhu, W. Xu, T. Zhang, “Combined Magnetic- and Circuit-level Enhancements for the Nondestructive Self-Reference Scheme of STT-RAM” IEEE
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[ISOCC]
2010
Y. Chen, H. Li, X. Wang, J. Park, “Applications of TMR Devices in Solid State Circuits and Systems” IEEE, pp. 252-255 DOI: 10.1109/SOCDC.2010.5682923
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[ISQED]
2010
Y. Chen, W. Tian, H. Li, X. Wang, W. Zhu, “Scalability of PCMO-based Resistive Switch Device in DSM Technologies” IEEE, pp.327-332 DOI: 10.1109/ISQED.2010.5450447
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[MWSCAS]
2010
Y. Chen, H. Li, Z. Sun, X. Wang, W. Zhu, G. Sun, Y. Xie, “Access Scheme of Multi-Level Cell Spin-Transfer Torque Random Access Memory and Its Optimization” IEEE, pp. 1109-1112 DOI: 10.1109/MWSCAS.2010.5548848
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[MWSCAS]
2010
H. Li, Y. Chen, , “Emerging Non-Volatile Memory Technologies ? From Materials, to Device, Circuit, and Architecture” IEEE, pp. 1-4 DOI: 10.1109/MWSCAS.2010.5548590
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[BSD]
2010
Z. Sun, H. Li, Y. Chen, X. Wang, “Magnetic Bio-sensing based on Spintronic Memristor”

[EDL]
2009
X. Wang, Y. Chen, H. Xi, H. Li, D. V. Dimitrov, “Spintronic Memristor through Spin Torque Induced Magnetization Motion” IEEE, pp. 294-297 DOI: 10.1109/LED.2008.2012270
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[Journal of Physics D: Applied Physics]
2009
H. Xi, X. Wang, Y. Chen, P. Ryan, “Ordering of Magnetic Nanoparticles in Bilayer Structures” JPD DOI: 10.1088/0022-3727/42/1/015006
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[TACO]
2009
C.-K. Koh, W.-F. Wong, Y. Chen, H. Li, “Tolerating Process Variations in Large, Set Associative Caches: The Buddy Cache” ACM, Volume 6 Issue 2, Article No. 8 DOI: 10.1145/1543753.1543757
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[TVLSI]
2009
Y. Chen, H. Li, C.-K. Chen, K. Roy, “Gated Decap: Gate Leakage Control of On-chip Decoupling Capacitors in Scaled Technologies” IEEE, pp. 775 – 778 DOI: 10.1109/CICC.2005.1568783
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[DAC]
2009
W. Xu, Y. Chen, X. Wang, T. Zhang, “Improving STT MRAM Storage Density through Smaller-Than-Worst-Case Transistor Sizing” ACM, Pages 87-90 DOI: 10.1145/1629911.1629936
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[DATE]
2009
H. Li, Y. Chen, , “An Overview of Non-Volatile Memory Technology and the Implication for Tools and Architectures” IEEE, pp. 731 – 736 DOI: 10.1109/DATE.2009.5090761
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[HPCA]
2009
G. Sun, X. Dong, Y. Xie, J. Li, Y. Chen, “A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs” IEEE, pp. 239-249 DOI: 10.1109/HPCA.2009.4798259
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[ICCD]
2009
C.-K. Koh, W.-F. Wong, Y. Chen, H. Li, “The Salvage Cache: A Fault-tolerant Cache Architecture for Next-generation Memory Technologies” IEEE, pp. 268 – 274 DOI: 10.1109/ICCD.2009.5413145
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[ISVLSI]
2009
H. Li, H. Xi, Y. Chen, J. Stricklin, X. Wang, T. Zhang, “Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration” IEEE, pp. 217-222 DOI: 10.1109/ISVLSI.2009.17
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[NANOARCH]
2009
Y. Chen, X. Wang, , “Compact Modeling and Corner Analysis of Spintronic Memristor” IEEE, pp. 7-12 DOI: 10.1109/NANOARCH.2009.5226363
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2008
H. Li, R. Patel, K. Sit, Z. Tang , S. Jamshidi, “Design for Low Power” CRC Press DOI: 978-08-493-0885-7
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[DAC]
2008
X. Dong, X. Wu, G. Sun, Y. Xie, Y. Chen, H. Li, “Circuit and Microarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Replacement” IEEE, pp. 554 – 559
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[InterMag]
2008
X. Wang, Y. Chen, H. Li, H. Liu, D. Dimitrov, “Spin Torque Random Access Memory down to 22nm Technology” IEEE, pp. 2479-2482 DOI: 10.1109/TMAG.2008.2002386
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[ISCAS]
2008
W. Xu, T. Zhang, Y. Chen, “Spin-Transfer Torque Magnetoresistive Content Addressable Memory (CAM) Cell Structure Design with Enhanced Search Noise Margin” IEEE

[ISQED]
2008
Y. Chen, X. Wang, H. Li, H. Liu, D. Dimitrov, “Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)” IEEE, pp. 684-690 DOI: 10.1109/ISQED.2008.4479820
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[TMAG]
2008
X. Wang, Y. Chen, H. Li, D. Dimitrov, H. Liu, “Spin Torque Random Access Memory Down to 22nm Technology” IEEE, pp. 2479 – 2482 DOI: 10.1109/TMAG.2008.2002386
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[ICCD]
2007
C.-K. Koh, W.-F. Wong, Y. Chen, H. Li, “VOSCH: Voltage Scaled Cache Hierarchies” IEEE, pp.496 – 503 DOI: 10.1109/ICCD.2007.4601944
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[ISLPED]
2007
Y. Chen, H. Li, J. Li, C.-K. Koh, “Variable-latency Adder (VL-Adder): New Arithmetic Circuit Design Practice to Overcome NBTI” ACM, Pages 195-200 DOI: 10.1145/1283780.1283822
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[ISQED]
2007
H. Li, C.-K. Koh, V. Balakrishnan, Y. Chen, “Statistical Timing Analysis Considering Spatial Correlations” IEEE, pp. 102-107
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[ASP-DAC]
2006
H. Li, Y. Chen, K. Roy, C.-K. Koh, “SAVS: A Self-adaptive Variable Supply-voltage Technique for Process-tolerant and Power-efficient Multi-issue Superscalar Processor Design” IEEE, N/A DOI: 10.1109/ASPDAC.2006.1594675
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[TVLSI]
2005
Y. Chen, K. Roy, C.-K. Koh, “Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors” IEEE, pp.75 – 85 DOI: 10.1109/TVLSI.2004.840404
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[TVLSI]
2005
H. Li, C.-Y. Cher, T. N. Vijaykumar, K. Roy, “Combined Circuit and Architectural Level Variable Supply-Voltage Scaling for Low Power” IEEE, pp.564 – 576 DOI: 10.1109/TVLSI.2005.844295
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[TVLSI]
2005
Y. Chen, H. Li, K. Roy, C.-K. Koh, “Gated Decap: Gate Leakage Control of On-chip Decoupling Capacitors in Scaled Technologies” IEEE, pp.1749 – 1752 DOI: 10.1109/TVLSI.2008.2007843
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[ICCAD]
2005
W.-C.D. Lam, J. Jain, C.-K. Koh, V. Balakrishnan, Y. Chen, “Statistical Based Link Insertion for Robust Clock Network Design” IEEE, pp.588 – 591 DOI: 10.1109/ICCAD.2005.1560134
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[ISLPED]
2005
Y. Chen, H. Li, K. Roy, C.-K. Koh, “Cascaded Carry-Select Adder (C2SA): A New Structure for Low-Power CSA Design” IEEE, pp.115 – 118 DOI: 10.1109/LPE.2005.195498
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[ISQED]
2005
D. Kung, Y. Chen, K. Roy, “Power Supply Noise-aware Scheduling and Allocation for DSP Synthesis” IEEE, pp.48 – 53 DOI: 10.1109/ISQED.2005.97
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[TVLSI]
2004
H. Li, S. Bhunia, Y. Chen, T. N. Vijaykumar, K. Roy, “DCG: Deterministic Clock Gating For Low-Power Microprocessor Design” IEEE, pp.245 – 254 DOI: 10.1109/TVLSI.2004.824307
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[ASP-DAC]
2004
Y. Chen, K. Roy, C.-K. Koh, “Priority Assignment Optimization for Minimization of Current Surge in High Performance Power Efficient Clock-gated Microprocessor” IEEE, pp.894 – 899 DOI: 10.1109/ASPDAC.2004.1337722
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[JSSC]
2003
Y. Chen, K. Roy, C.-K. Koh, “A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron” IEEE, pp.319 – 328 DOI: 10.1109/JSSC.2002.807414
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[HPCA]
2003
H. Li, S. Bhunia, Y. Chen, T.N.Vijaykumar, K. Roy, “Deterministic Clock Gating for Microprocessor Power Reduction” IEEE, pp.113 – 122 DOI: 10.1109/HPCA.2003.1183529
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[ISLPED]
2003
Y. Chen, K. Roy, C.-K. Koh, “Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-gated Microprocessors” IEEE, pp. 229 – 234 DOI: 10.1109/LPE.2003.1231867
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[MICRO]
2003
H. Li, C.-Y. Cher, T. N. Vijaykumar, K. Roy, “VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power” IEEE, pp. 19-28 DOI: 10.1109/MICRO.2003.1253180
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[Chinese Journal of Laser]
2002
Y. Chen, L. Zhang, C. Fan, “Beat Phenomena and Its Suppression in Cascaded Gain-clamped EDFAs”

[ATS]
2002
S. Bhunia, H. Li, K. Roy, “A High Performance IDDQ Testable Cache for Scaled CMOS Technologies” IEEE, pp. 157-162 DOI: 10.1109/ATS.2002.1181704
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[DAC]
2002
A. Agrawal, H. Li, K. Roy, “DRG-Cache: A Data Retention Gated-Ground Cache for Low Power” IEEE, pp. 473-478 DOI: 10.1109/DAC.2002.1012671
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[DATE]
2002
Y. Chen, V. Balakrishnan, C.-K. Koh, K. Roy, “Model Reduction in the Time-domain using Laguerre Polynomials and Krylov Methods” IEEE, pp.931 – 935 DOI: 10.1109/DATE.2002.998411
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[IEEE Proceeding of Optoelectronics]
2001
Y. Chen, L. Zhang, C. Fan, “Beat Phenomena in Cascaded All-Optical Gain-Clamped Erbium-Doped Fiber Amplifiers” IET, pp.161 – 164 DOI: 10.1049/ip-opt:20010518
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[Microelectronics ]
2000
H. Li, J. Wang, , “An Optimal Strategy for Parameter Extraction of BSIM3V3 Model” Microelectronics , volume 30, issue 6, pages 387-390
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[ICCT]
2000
Y. Chen, L. Zhang, Z. Jiang, Q. Yu, C. Fan, “Suppression of Stimulated Brillouin Scattering induced by the Compensating Signal in All-Optical Gain-Clamped EDFA” IEEE, vol.1 pp. 203 – 205 DOI: 10.1109/ICCT.2000.889198
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